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參數(shù)資料
| 型號： | AD9854 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | CMOS 300MHz Quadrature Complete-DDS |
| 中文描述： | 300MHz CMOS正交DDS數(shù)字合成器 |
| 文件頁數(shù)： | 15/28頁 |
| 文件大小： | 589K |
| 代理商： | AD9854 |
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AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
As with the ramped FSK mode, a non-linear chirp is
created by constructing the progression in a piece-wise
fashion.
Chirp operation of the AD9854 is less automated than
the ramped FSK mode particularly regarding the
destination frequency, which is not actually specified in
the programming registers. It is incumbent upon the
user to know when the destination frequency has been
achieved. The value of the 48-bit Delta Frequency
Word(s) and the 20-bit Ramp Rate Clock value(s) are
all that are needed to calculate when the destination
frequency will occur. It is up to the user to determine
what occurs when the destination frequency is reached.
Here are a few of the choices:
7/16/99 REV.PRA
15
a)
Stop and hold at the destination frequency using
the HOLD pin, Pin29, or by loading zero into the
Frequency Accumulator register of ACC 1. Either
method will work.
b)
Stop, hold and then ramp-down the output
amplitude using the digital multiplier stages and
the Shaped Keying pin, Pin30, or via program
register control (address’s 21 – 24 hex).
c)
Stop and abruptly terminate the transmission using
the CLR ACC 2 bit.
d)
Continue chirp by reversing direction and returning
to the same or another destination frequency in a
linear or user-directed manner. If this involves
going down in frequency then a negative 48-bit
Delta Frequency Word (the MSB is set to “1”)
must be loaded into registers 10 – 15 hex. Any
decreasing frequency step of the Delta Frequency
Word requires the MSB to be set to logic high.
e)
Continue chirp by immediately returning to the F1
beginning frequency in a saw tooth fashion and
repeat the previous chirp process again. This is
where CLR ACC1 control bit is used. An
automatic chirp can be setup using the 32 bit
Update Clock to issue CLR ACC1 commands at
precise time intervals.
The figure below shows how the various chirp
registers, accumulators, etc. are connected.
I/O Port Buffers
– 100 MHz, 8-bit parallel or 10
MHz serial loading, SPI compatible. The programming
mode is selected externally via the serial/parallel (S/P
Select) pin. I/O Buffers can be written to, or read from,
according to the signals supplied to the Read
(RDB)and Write pins (WRB) and the 6-bit address
(A0 – A5) in the parallel mode or to CSB, SCLK and
SDIO pins in the Serial mode. Data in the I/O Port
Buffers is stored until overwritten by changes in
program instructions supplied by the user or until
power is removed. An I/O Update clocks-in the data
from the I/O Buffers to the DDS Programming
Registers where it is executed.
AM
– amplitude modulation of the I & Q DACs is
possible using the I/O port to control 12-bit digital
multiplier stages that precede the DACs. The
multipliers can also be used to set the DAC outputs
48-Bit Delta-
Frequency
Word
Accu 1
Accu 2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9854/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For IC Digital Synthesizer Single 制造商:Analog Devices 功能描述:Direct Digital Synthesizer IC (DDS) |
| AD9854/PCBZ | 功能描述:BOARD EVAL FOR AD9854 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| AD9854ASQ | 制造商:Analog Devices 功能描述:IC DDS SYNTHESIZER |
| AD9854ASQZ | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP 制造商:Analog Devices 功能描述:Communication IC |
| AD9854AST | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP Tray 制造商:Rochester Electronics LLC 功能描述:200 MHZ QUADRATURE DDS SYNTHESIZER - Tape and Reel 制造商:Analog Devices 功能描述:IC SEMICONDUCTOR ((NS)) |
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