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參數資料
| 型號： | AD9854 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | CMOS 300MHz Quadrature Complete-DDS |
| 中文描述： | 300MHz CMOS正交DDS數字合成器 |
| 文件頁數： | 19/28頁 |
| 文件大小： | 589K |
| 代理商： | AD9854 |
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AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
Programming the AD9854/52
7/16/99 REV.PRA
19
The AD9854/52 Register Layout, shown in Table 1,
contains the information that programs the chip for the
desired functionality. While many applications will
require very little programming to configure the
AD9854/52, some will make use of all 12 registers that
are accessible. The AD9854/52 supports an 8-bit
parallel IO operation or a SPI compatible serial IO
operation. All registers accessible can be written and
read back in either IO operating mode.
An external pin, SPSELECT, is used to configure the
IO mode. Systems that use the parallel IO mode must
tie the SPSELECT pin to VDD. Systems that operate
in the serial IO mode must tie the SPSELECT pin to
GND.
Regardless of mode, the IO port data is written to a
buffer memory that does NOT affect operation of the
part until the contents of the buffer memory is
transferred to the register bank. This transfer of
information occurs synchronous to the system clock
and occurs in one of two ways, 1) internally controlled
at a rate programmable by the user or, 2) externally
controlled by the user. IO operations can occur in the
absence of REFCLK but the data cannot be moved
from the buffer memory to the register bank without
REFCLK. See the Update Clock Operation section of
this document for details.
Buffer
Memory
Latches
buf_outRampRate<7:0>
buf_outRampIMult<15:0>
buf_CTL<31:0>
buf_RRC<19:0>
buf_delPh<47:0>
buf_udClk<31:0>
buf_ftw2<47:0>
buf_ftw1<47:0>
buf_phAdjust2<13:0>
buf_phAdjust1<13:0>
Addr<5:0>
D<7:0>
___
WR
___
RD
Update Clock Logic
UPDATE_CLK
sysclk
hold
T
IntUpdateActive
Register
Bank
outRampQMult<15:0>
outRampIMult<15:0>
CTL<31:0>
RRC<19:0>
delPh<47:0>
ftw2<47:0>
ftw1<47:0>
phAdjust2<13:0>
phAdjust1<13:0>
updateRegs
AD9854/52 IO Port Block Diagram
buf_outRampQMult<15:0>
buf_QDAC<11:0>
sysclk
QDAC<11:0>
outRampRate<7:0>
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9854/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For IC Digital Synthesizer Single 制造商:Analog Devices 功能描述:Direct Digital Synthesizer IC (DDS) |
| AD9854/PCBZ | 功能描述:BOARD EVAL FOR AD9854 RoHS:是 類別:編程器，開發系統 >> 評估演示板和套件 系列:AgileRF™ 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| AD9854ASQ | 制造商:Analog Devices 功能描述:IC DDS SYNTHESIZER |
| AD9854ASQZ | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP 制造商:Analog Devices 功能描述:Communication IC |
| AD9854AST | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP Tray 制造商:Rochester Electronics LLC 功能描述:200 MHZ QUADRATURE DDS SYNTHESIZER - Tape and Reel 制造商:Analog Devices 功能描述:IC SEMICONDUCTOR ((NS)) |
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