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參數資料
| 型號： | AD9898KCPRL-20 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | TVPS00RF-21-41S W/ PC CON |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | MO-220-VKKD-2, LFCSP-48 |
| 文件頁數： | 10/52頁 |
| 文件大小： | 557K |
| 代理商： | AD9898KCPRL-20 |
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REV. 0
–10–
AD9898
Table I. Control Register Address Map (Register Names Are Subject to Change)
Bit
Width
Default
Value
Register
Name
Address
Content
Register Description
00
(23:0)
23
000000
SW_RESET
Software Reset = 000000. (Reset all registers to default.)
01
(23:21)
20
(19:18)
17
16
(15:14)
13
3
1
2
1
1
2
1
0
0
1
1
0
0
0
Unused
Unused. Test Mode. Should be set = 0.
Unused
Masking Polarity for H1 during blanking period (0 = Low, 1 = High)
External SYNC Active Polarity (0 = Active Low)
Unused
High Precision Shutter Mode Operation (0 = Single Pulse, 1 = Multiple
Pulse)
Suppress First SUBCK after Last VSG Line Pulse (0 = No Suppression,
1 = Suppression of 1 SUBCK)
Unused
Selects MSHUT Pattern (See Figure 44) (0 = MSHUTPAT0,
1 = MSHUTPAT1, 2 = MSHUTPAT2, 3 = MSHUTPAT3)
MSHUT Masking of VGATE Input (0 = MSHUT does not mask
VGATE, 1 = MSHUT does mask VGATE)
MSHUT Masking of SUBCK (0 = MSHUT does not mask SUBCK,
1 = MSHUT does mask SUBCK)
CLPOB Control (0 = CLPOB OFF, 1 = CLPOB ON)
CLPOB CCD Region Control (See Table XII)
Unused
VD Synchronous/Asynchronous Mode Setting (0 = VD Synchronous,
1 = VD Asynchronous)
HBLKMASK
SYNCPOL
SUBCKMODE_HP
12
1
0
SUBCKSUPPRESS
(11:10)
(9:8)
2
2
0
0
MSHUTPAT
7
1
0
MSHUT/VGATE_EN
6
1
0
MSHUT/SUBCK_EN
5
4
(3:1)
0
1
1
3
1
1
1
0
0
CLP_CONT
CLP_MODE
VDMODE
02
(23:22)
(21:16)
(15:14)
(13:8)
(7:6)
(5:0)
2
6
2
6
2
6
0
0x34
0
0x18
0
0x0B
Unused
SHD Sample Location
Unused
SHP Sample Location
DCLK Pulse Adjustment
Data Output [9:0] Phase Adjustment
SHDLOC
SHPLOC
DCLKPHASE
DOUTPHASE
03
(23:17)
16
(15:14)
(13:8)
(7:6)
(5:0)
7
1
2
6
2
6
0x00
0
0
0x00
0
0x10
Unused
Retimes the H1 HBLK to Internal Clock
Unused
H1 Positive Edge Location
Unused
RG Negative Edge Location
H1BLKRETIME
H1POSLOC
RGNEGLOC
04
(23:22)
(21:16)
(14:12)
2
6
3
0
0x20
5
Unused
Black Clamp Level
H2 Drive Strength (0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,
4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA)
Unused
H1 Drive Strength (0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,
4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA)
Unused
RG Drive Strength (0 = Off, 1 = 2.15 mA, 2 = 4.2 mA, 3 = 6.45 mA,
4 = 8.6 mA, 5 = 10.75 mA, 6 = 12.9 mA, 7 = 15.05 mA)
REFBLACK
H2DRV
11
(10:8)
1
3
0
5
H1DRV
(7:3)
(2:0)
5
3
0x00
2
RGDRV
05
(23:10)
9
8
(7:2)
1
14
1
1
6
1
0x0000
0
0
00
0
Unused
AFE Standby (0 = Standby , 1 = Normal Operation)
Digital Standby (0 = Standby , 1 = Normal Operation)
Unused
Internal OUTCONT Signal Control (0 = Digital Outputs held at fixed
dc level, 1 = Normal Operation)
External OUTCONT Signal Input Pin 43 Control (0 = Pin Enabled,
1 = Pin Disabled)
AFESTBY
DIGSTBY
OUTCONT_REG
0
1
1
OUTCONT_ENB
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