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參數(shù)資料
| 型號： | AD9898KCPRL-20 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | TVPS00RF-21-41S W/ PC CON |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | MO-220-VKKD-2, LFCSP-48 |
| 文件頁數(shù)： | 51/52頁 |
| 文件大小： | 557K |
| 代理商： | AD9898KCPRL-20 |
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REV. 0
AD9898
–51–
CIRCUIT LAYOUT INFORMATION
The AD9898 typical circuit connection is shown in Figure 58.
The PCB layout is critical to achieving good image quality from
the AD9898. All of the supply pins, particularly the AVDD,
TCVDD, RGVDD, and HVDD supplies, must be decoupled to
ground with good quality high frequency chip capacitors. The
decoupling capacitors should be located as close as possible to
the supply pins and should have a very low impedance path to a
continuous ground plane. There should also be a 4.7
μ
F or
larger value bypass capacitor for each main supply—AVDD,
RGVDD, HVDD, and DRVDD—although this is not necessary
for each individual pin. For most applications, it is easier to
share the supply for RGVDD and HVDD, which may be done
as long as the individual supply pins are separately bypassed. A
separate 3 V supply may also be used for DRVDD, but this
32
31
30
29
28
27
26
25
33
35
34
36
13
14
15 16
17 18
19
20
21
22
23
24
PIN 1
(TOP VIEW
CCDIN
AVDD
CLI
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
AD9898
10
DATA
OUTPUTS
3V
ANALOG
SUPPLY
3V
DRIVER
SUPPLY
DRVDD
DRVSS
REFB
REFT
AVSS
TCVDD
TCVSS
RGVDD
D
F
R
SL
SDATA
V
O
V
M
S
4.7 F
3
V1–V4
VSG1, VSG2
SUBCK
TO V-DRIVER
0.1 F
0.1 F
0.1 F
0.1 F
3
DCLK1, FD/DCLK2, HD, VD
TO MECHANICAL SHUTTER CIRCUIT
TO STROBE CIRCUIT
3V
ANALOG SUPPLY
0.1 F
H
H
R
H
V
H
H
H2, H1, RG
INPUT CLOCK
SCK
S
D
D
S
V
4.7 F
0.1 F
CCD SIGNAL
3V
ANALOG SUPPLY
1.0 F
1.0 F
1
2
3
4
5
6
7
8
9
10
11
12
48
47
46 45
44 43
42
41
40
39
38
37
4
0.1 F
3V
ANALOG SUPPLY
SERIAL
INTERFACE
V
V
V
V
VSUB TO CCD
EXTERNAL SYNC FROM ASIC/DSP
OUTCONT
10k
3V
DRIVER
SUPPLY
7
Figure 58. Typical Circuit Configuration
supply pin should still be decoupled to the same ground plane
as the rest of the chip. A separate ground for DRVSS is not
recommended.
The analog bypass pins (REFB, REFT) also should be carefully
decoupled to ground as close as possible to their respective pins.
The analog input (CCDIN) capacitor also should be located
close to the pin.
The H1, H2, and RG traces should be designed to have low
inductance to avoid excessive distortion of the signals. Heavier
traces are recommended because of the CCD’s large transient
current demand on H1 and H2. When possible, physically
locating the AD9898 closer to the CCD will reduce the induc-
tance on these lines. As always, the routing path should be as
direct as possible from the AD9898 to the CCD.
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