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參數資料
| 型號： | AD9898KCPRL-20 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | TVPS00RF-21-41S W/ PC CON |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | MO-220-VKKD-2, LFCSP-48 |
| 文件頁數： | 11/52頁 |
| 文件大小： | 557K |
| 代理商： | AD9898KCPRL-20 |
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REV. 0
AD9898
–11–
Table I. Control Register Address Map (Register Names Are Subject to Change)
Bit
Width
Default
Value
Register
Name
Address
Content
Register Description
0A
23
22
(21:16)
(15:12)
(11:10)
1
1
6
4
2
1
1
4
2
1
1
0
0
0x00
0
0
0
0
C
3
0
0
Unused
FD Polarity Control (0 = Low, 1 = High)
VSG Masking (See Table XXIII)
External SYNC Setting
Super Vertical Repetition Mode
H Pulse Blanking Extend Control
H Pulse Control during Blanking
SPAT Logic Setting (See Table XX)
Second V Output Setting (10 = Output Repetition 1)
SPAT Control (0 = SPAT Disable, 1 = SPAT Enable)
Mode Control Bit (0 = Mode_A, 1 = Mode_B)
FDPOL
VSGMASK
SYNCCNT
SVREP_MODE
HBLKEXT
HPULSECNT
SPATLOGIC
SVOS
SPAT_EN
MODE
(VD
SyncReg)
*
9
8
(7:4)
(3:2)
1
0
0B
(23:22)
21
20
(19:17)
2
1
1
3
1
0
1
1
0
0
Unused
SUBCK Output Enable Control (0 = Disable, 1 = Enable)
VSG Output Enable Control (0 = Disable, 1 = Enable)
Unused
STROBE Output Control (0 = STROBE Output Held Low,
1 = STROBE Output Enabled)
Unused
High Precision Shutter SUBCLK Pulse Position/Number
Unused
Total Number of SUBCKs per Field
SUBCK_EN
VSG_EN
(VD
SyncReg)
*
16
STROBE_EN
15
(14:12)
11
(10:0)
1
3
1
11
0
0
0
0x7FF
SUBCKNUM_HP
SUBCKNUM
0C
(23:21)
20
(19:18)
17
3
1
2
1
1
1
3
1
11
0
0
0
0
0
0
0
0
0x000
Unused
MSHUT Initialize (1 = Forces MSHUT Low)
Unused
Unused
MSHUT Control ( 0 = MSHUT Held at Last State, 1 = MSHUT Output)
Unused
MSHUT Position during High Precision Operation
Unused
MSHUT Position during Normal Operation
MSHUTINIT
(VD
SyncReg)
*
16
MSHUTEN
15
(14:12)
11
(10:0)
MSHUTPOS_HP
MSHUTPOS
0D
(23:17)
16
(15:11)
7
1
5
11
Unused
VSUB Active Polarity (0 = Low, 1 = High)
Unused
VSUB Toggle Position. Active starting line in any field.
0
VSUBPOL
(VD
SyncReg)
*
(10:0)
0x000
VSUBTOG
0E
(23:21)
20
(19:18)
17
3
1
2
1
1
6
10
0
0
0
0
0
0x00
0x000
Unused
Unused. Test Mode. Should be set = 0.
Unused
Unused. Test Mode. Should be set = 0.
Unused. Test Mode. Should be set = 0.
Unused
VGA Gain
(VD
SyncReg)
*
16
(15:10)
(9:0)
VGAGAIN
D5
(23:4)
3
20
1
0x00000
1
Unused
DCLK2 Selector (0 = Select Internal FD Signal to be Output on FD/
DCLK2 Pin 16, 1 = Select CLI to be Output on FD/DCLK2 Pin 16)
DCLK1 Selector (0 = Select DLL Version for DCLK1 Output,
1 = Select CLI for DCLK1 Output)
Input Clock Divider (0 = No Division, 1 = 1/2, 2 = 1/3, 3 = 1/4)
DCLK2SEL
2
1
0
DCLK1SEL
(1:0)
2
0
CLKDIV
D6
(23:1)
0
23
1
0x000000
1
Unused
Operating Mode ( 0 = Master Mode, 1 = Slave Mode)
SLAVE_MODE
*
This register defaults to VD synchronous mode type at power up. VD sync type registers do not get updated until the first falling edge of VD is asserted after the
register has been programmed. VD sync type registers can be programmed to be asynchronous registers by setting VDMODE = 1 (Addr 0x01).
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