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參數資料
| 型號： | AD9898KCPRL-20 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | TVPS00RF-21-41S W/ PC CON |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | MO-220-VKKD-2, LFCSP-48 |
| 文件頁數： | 35/52頁 |
| 文件大小： | 557K |
| 代理商： | AD9898KCPRL-20 |
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REV. 0
AD9898
–35–
Special Vertical Timing (SPAT)
The AD9898 provides additional special vertical timing (SPAT)
generation, which is output in the same line as the VSG pulse.
The SPAT timing allows for configuring a second vertical out-
put pulse in the VSG line. Tables XIX and XX list the registers
used to generate the SPAT timing.
Figures 35 and 36 show how the SPAT timing can be either an
AND case or an OR case, depending on the value set in the
SPATLOGIC register. As these figures show, the internal SPAT
timing for the AND case will start High and then go Low at the
first VxSPAT_TOG1 position. In the OR case, the internal
Table XIX. HD and VD Registers
Register
Name
Bit
Width
Reference
Counter
Range
Pixels
Register Type
Description
SPAT_EN
1
Control (Addr 0x0A)
SPAT Enable Control
(0 = SPAT Disabled, 1 = SPAT Enabled)
SPAT Logic Setting
Polarity Change Position Start for V1 SPAT
Polarity Change Position End for V1 SPAT
Polarity Change Position Start for V2 SPAT
Polarity Change Position End for V2 SPAT
Polarity Change Position Start for V3 SPAT
Polarity Change Position End for V3 SPAT
Polarity Change Position Start for V4 SPAT
Polarity Change Position End for V4 SPAT
SPATLOGIC
V1SPAT_TOG1
V1SPAT_TOG2
V2SPAT_TOG1
V2SPAT_TOG2
V3SPAT_TOG1
V3SPAT_TOG2
V4SPAT_TOG1
V4SPAT_TOG2
4
13
13
13
13
13
13
13
13
Control (Addr 0x0A)
Mode_Reg(5)
Mode_Reg(5)
Mode_Reg(6)
Mode_Reg(6)
Mode_Reg(6 and 7)
Mode_Reg(7)
Mode_Reg(7)
Mode_Reg(7 and 8)
ST
ST
ST
ST
ST
ST
ST
ST
0–8192
0–8192
0–8192
0–8192
0–8192
0–8192
0–8192
0–8192
1. THE VxSPAT_TOG1 AND VxSPAT_TOG2 REGISTERS REFERENCE THE 13-BIT ST COUNTER.
2. THE INTERNAL SPAT TIMING IS APPLIED IN THE SAME LINE AS THE VSGx PULSE.
PROGRAMMABLE CLOCK POSITIONS
1. VxSPAT_TOG1 (PROGRAMMABLE AT MODE_REGs).
2. VxSPAT_TOG2 (PROGRAMMABLE AT MODE_REGs).
HD
13-BIT
ST COUNTER
(FIXED)
INTERNAL V2
WITHOUT
SPAT APPLIED
INTERNAL SPAT
TIMING FOR V2 WITH
SPATLOGIC = 1
V2 OUTPUT WITH
SPAT APPLIED
VSGx
VD
2
1
Figure 35. SPAT Example Applied to V2 with SPATLOGIC = xx1x
SPAT timing will initially start Low and then toggle High at the
first VxSPAT_TOG1 position. This provides the ability to
output the second vertical pulse when the internal Vx pulse is
in both High and Low states.
Table XX. SPATLOGIC Register (Addr 0x0A)
SPATLOGIC [3:0]
3
2
V4
V3
Description
1
V2
0
V1
0 = OR, 1 = AND
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