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參數(shù)資料
| 型號： | AD9898KCPRL-20 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | TVPS00RF-21-41S W/ PC CON |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | MO-220-VKKD-2, LFCSP-48 |
| 文件頁數(shù)： | 26/52頁 |
| 文件大小： | 557K |
| 代理商： | AD9898KCPRL-20 |
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REV. 0
–26–
AD9898
Controlling CLPOB Clamp Pulse Outputs
The registers in Table XII are used for programming the CLPOB
pulse, which will be disabled in all CCD regions by setting
CLPCNT = 0. The CLPTOGx (x = 0, 1) are used to set the
CLPOB toggle positions. The CLPENx (x = 0, 1, 2, 3, and 4)
are used to enable or disable the CLPOB pulse separately in
each CCD region when CLPMODE = 0. The CLPEN regis-
ters have no effect if CLPMODE = 1. In this case, the CLPOB
pulse will be asserted in all CCD regions, regardless of the value
set in the CLPENx registers.
Figure 22 shows an example of the CLPOB pulse being disabled
in CCD Regions 1 and 3 by setting CLPEN1 = 1 and CLPEN3
= 1. Note that the CLPOB pulse remains disabled in the first
line of the following CCD region.
1
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2
3
4
5
A
B
VD
HD
CLPOB
CLPMASK
(INTERNAL)
PROGRAMMING POSITIONS
1. SCP0 = 0 (FIXED), CLPEN0 = 1
2. SCP1 = 3, CLPEN1 = 0
3. SCP2 = 4, CLPEN2 = 1
4. SCP3 = 5, CLPEN3 = 0
5. SCP4 = 1, CLPEN4 = 1
NOTE
THE INTERNAL CLPMASK SIGNAL EXTENDS ONE EXTRA HD CYCLE FROM THE TIME WHEN THE
CLPMASK PERIOD CHANGES FROM LOW TO HIGH. AS A RESULT, ONE ADDITIONAL CLPOB PULSE
IS MASKED, AS SHOWN AT POSITIONS A AND B.
1
Figure 22. CLPOB Outputs with CLPMODE = 0
*
SCP0 is not a programmable register and therefore is not listed in the register
map tables. SCP0 is a fixed sequence and always starts at the falling edge of
VD. Although this register is not programmable, the CLPEN0 register is still
used to enable or disable the CLPOB pulse for the SCP0 region.
Table XIII. SCP and CLPEN
SCP[4:1]
CLPEN[4:0]
SCP0
*
SCP1
SCP2
SCP3
SCP4
CLPEN0
CLPEN1
CLPEN2
CLPEN3
CLPEN4
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