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參數資料
| 型號： | AD9898KCPRL-20 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | TVPS00RF-21-41S W/ PC CON |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | MO-220-VKKD-2, LFCSP-48 |
| 文件頁數： | 8/52頁 |
| 文件大小： | 557K |
| 代理商： | AD9898KCPRL-20 |
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REV. 0
–8–
AD9898
SPECIFICATION DEFINITIONS
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every
code must have a finite width. No missing codes guaranteed to
10-bit resolution indicates that all 1024 codes, respectively,
must be present over all operating conditions.
Peak Nonlinearity
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9898 from a true straight
line. The point used as zero scale occurs 1/2 LSB before the
first code transition. Positive full scale is defined as a level 1
1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular output code to the
true straight line. The error is then expressed as a percentage of
the 2 V ADC full-scale signal. The input signal is always appro-
priately gained up to fill the ADC’s full-scale range.
R
AVDD
AVSS
AVSS
Figure 1. CCDIN
DVDD
DVSS
DRVSS
DRVDD
THREE-
STATE
DATA
DOUT
Figure 2. Digital Data Outputs
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship 1 LSB =
(ADC Full Scale/2
N
codes) where N is the bit resolution of the
ADC. For the AD9898, 1 LSB is 2 mV.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. The PSR specification is calculated from the change in the
data outputs for a given step change in the supply voltage.
EQUIVALENT INPUT CIRCUITS
330
DVDD
DVSS
Figure 3. Digital Inputs
HVDD OR
RGVDD
HVSS OR RGVSS
ENABLE
RG,
H1–H2
OUTPUT
Figure 4. H1–H2, RG Drivers
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