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參數資料
| 型號： | AD9898KCPRL-20 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | TVPS00RF-21-41S W/ PC CON |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | MO-220-VKKD-2, LFCSP-48 |
| 文件頁數： | 25/52頁 |
| 文件大小： | 557K |
| 代理商： | AD9898KCPRL-20 |
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REV. 0
AD9898
–25–
HORIZONTAL CLAMPING AND BLANKING
The AD9898’s horizontal clamping and blanking pulses are
programmable to suit a variety of applications. Similar to verti-
cal timing generation, individual sequences are defined for each
signal and are then organized into multiple regions during
image readout. This allows the dark pixel clamping and blanking
patterns to be changed at each stage of the readout to accommo-
date different image transfer timing and high speed line shifts.
Controlling CLPOB Clamp Pulse Timing
The AFE horizontal CLPOB pulse is generated based on the
12-bit gray code counter. Once the length of the 12-bit gray
code counter is set using the HDLEN register (Sys_Reg(12)),
CLPTOG1 and CLPTOG2 registers (Sys_Reg(15 and16)) can
be used to place the CLPOB pulse location, as shown in Figure 19.
Table XII lists all CLPOB registers that are used to configure
and control the placement and output of the CLPOB pulse.
The length of the last HD line is set using the HDLASTLEN
register (Sys_Reg(1)). Figure 20 shows that no CLPOB pulse
will be asserted when the last HD length set by HDLASTLEN
is shorter than the regular HD length set by HDLEN.
Figure 21 shows that no CLPOB pulse will be applied when the
last HD length set by HDLASTLEN is longer than the regular
HD length. Note that the CLPOB pulse is applied in the last
line only when HDLASTLEN = HDLEN.
LAST LINE
HD
CLPOB
Figure 20. Last HD Shorter Than Regular HD
LAST LINE
HD
CLPOB
Figure 21. Last HD Longer Than Regular HD
Table XII. CLPOB Registers
Register
Name
Bit
Width Register Type
Reference
Counter
Range
Description
CLP_CONT
CLP_MODE 1
1
Control (0x01)
Control(0x01)
CLPOB Control (0 = CLPOB Off, 1 = CLPOB On)
CLPOB CCD Region Control
(0 = Enable CLPENx Register Settings,
1 = Disable CLPENx Register Settings)
0–4095 Pixel Locations CLPOB Toggle Position 1 (Gray Code Number)
0–4095 Pixel Locations CLPOB Toggle Position 2 (Gray Code Number)
CLPOB Control for CCD Region 0
(0 = CLPOB Disabled, 1 = CLPOB Enabled)
CLPOB Control for CCD Region 1
(0 = CLPOB Disabled, 1 = CLPOB Enabled)
CLPOB Control for CCD Region 2
(0 = CLPOB Disabled, 1 = CLPOB Enabled)
CLPOB Control for CCD Region 3
(0 = CLPOB Disabled, 1 = CLPOB Enabled)
CLPOB Control for CCD Region 4
(0 = CLPOB Disabled, 1 = CLPOB Enabled)
CLPTOG1
CLPTOG2
CLPEN0
12
12
1
Sys_Reg(15)
Sys_Reg(15 and 16) HD
Mode_Reg(2)
HD
CLPEN1
1
Mode_Reg(2)
CLPEN2
1
Mode_Reg(2)
CLPEN3
1
Mode_Reg(2)
CLPEN4
1
Mode_Reg(2)
12-BIT
GRAY COUNTER
+ SETUP
VD
HD
PROGRAMMABLE CLOCK POSITIONS
1. CLPTOG1 (SYS_REG(15))
2. CLPTOG2 (SYS_REG(15 AND 16))
CLPOB
1
2
Figure 19. Location of CLPOB Using CLPTOG1 and CLPTOG2 Registers
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