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參數資料
| 型號： | AD9929 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with Precision Timing Generator |
| 中文描述： | CCD信號處理器精確時序發生器 |
| 文件頁數： | 11/64頁 |
| 文件大小： | 558K |
| 代理商： | AD9929 |
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AD9929
Table 8. Control Register Address Map
Rev. A | Page 11 of 64
Address
0x00
0x01
Content
(23:0)
23
Bit
Width
24
1
Default
Value
000000
0
Register Name
SW_RESET
Unused
Register Description
Software Reset = 000000 (Reset All Registers to Default )
Suppress XSUBCK (00 = No Suppression, 01 = Suppress First XSUBCK
After Last VSG Line Pulse, 10 = Suppress All XSUBCKs, Except Final
XSUBCK, 11 = No Suppression)
Test Mode. Should Be Set = 0
Masking Polarity for H1 During Blanking Period (0 = Low, 1 = High)
External SYNC Active Polarity (0 = Active Low)
High Precision Shutter Mode Operation
(0 = Single Pulse, 1 = Multiple Pulse)
Selects MSHUT Pattern. (See Figure 51)
(0 = Mshutpat0,1 = Mshutpat1,2 = Mshutpat2, 3 = Mshutpat3)
MSHUT Masking of VGATE Input (0 = MSHUT Does Not Mask VGATE,
1 = MSHUT Does Mask VGATE)
CLPOB Control (0 = CLPOB Off, 1 = CLPOB On)
CLPOB CCD Region Control (See Table 19)
VD Synchronous/Asynchronous Mode Setting
(0 = VD Synchronous, 1 = VD Asynchronous )
SHD Sample Location
SHP Sample Location
DCLK Pulse Adjustment
Data Output [11:0] Phase Adjustment
Retimes the H1 HBLK to Internal Clock
H1 Positive Edge Location
RG Negative Edge Location
Black Level Clamp
H2 Drive Strength (0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,
4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA)
H1 Drive Strength (0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,
4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA)
RG Drive Strength (0 = Off, 1 = 2.15 mA, 2 = 4.2 mA, 3 = 6.45 mA,
4 = 8.6 mA, 5 = 10.75 mA, 6 = 12.9 mA, 7 = 15.05 mA)
AFE Standby (0 = Standby, 1 = Normal Operation)
Digital Standby (0 = Standby, 1 = Normal Operation)
Internal OUTCONT Signal Control
(0 = Digital Outputs Held at Fixed DC Level, 1 = Normal Operation)
External OUTCONT Signal Input Pin 43 Control (0 = Pin Enabled,
1 = Pin Disabled)
(22:21)
2
XSUBCKSUPPRESS
(20:18)
17
16
(15:14)
3
1
1
2
0
1
0
0
Unused
HBLKMASK
SYNCPOL
Unused
13
1
0
XSUBCKMODE_HP
(12:10)
3
0
Unused
(9:8)
2
0
MSHUTPAT
7
1
0
MSHUT/VGATE_EN
6
5
4
(3:1)
1
1
1
3
0
1
1
0
Unused
CLPOB_CONT
CLPOB_MODE
Unused
0
1
0
VDMODE
0x02
0x03
0x04
(23:22)
(21:16)
(15:14)
(13:8)
(7:6)
(5:0)
(23:17)
16
(15:14)
(13:8)
(7:6)
(5:0)
(23:16)
15
2
6
2
6
2
6
7
1
2
6
2
6
8
1
0
0x34
0
0x18
0
0x0B
0x00
0
0
0x00
0
0x10
0x80
–
Unused
SHDLOC
Unused
SHPLOC
DCLKPHASE
DOUTPHASE
Unused
H1BLKRETIME
Unused
H1POSLOC
Unused
RGNEGLOC
REFBLACK
Unused
(14:12)
3
5
H2DRV
11
1
0
Unused
(10:8)
3
5
H1DRV
(7:3)
5
0x00
Unused
(2:0)
3
2
RGDRV
0x05
(23:10)
9
8
(7:2)
14
1
1
6
0x0000
0
0
00
Unused
AFESTBY
DIGSTBY
Unused
1
1
0
OUTCONT_REG
0
1
1
OUTCONT_ENB
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