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參數資料
| 型號： | AD9929 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with Precision Timing Generator |
| 中文描述： | CCD信號處理器精確時序發生器 |
| 文件頁數： | 58/64頁 |
| 文件大?。?/td> | 558K |
| 代理商： | AD9929 |
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AD9929
APPLICATIONS WHERE THE CLI CLOCK FREQUENCY CHANGES DURING OPERATION
The AD9929 must be reset, as described in Figure 69, if the CLI
clock frequency is changed during operation. The DCLK1
Rev. A | Page 58 of 64
output can become unstable if this reset sequence is not applied
after any changes in the CLI clock frequency.
3
1
2
t
DELAY
*
VD
(OUTPUT)
OUTPUTS
CL
OUTCONT
(INTERNAL
SIGNAL)
DIG_STBY
(REGISTER)
SERIAL
WRITES
DCLK1I
t
1
HD, VD, H1, (SUBCK = VH2)
0
FAST
FAST
SLOW
HD
(OUTPUT)
4
(V1, V2, V3, V4 = VL), H2, STROBE, MSHUT
REGION B
REGION A
REGION C
SERIAL PROGRAMMING STEPS MUST BE FOLLOWED WHEN THE CLI CLOCK FREQUENCY CHANGES
1. OUTCONT_REG = 0
2. DIG_STBY = 0
3. DIG_STBY = 1
4. OUTCONT_REG = 1
NOTES ABOUT REGIONS A, B, AND C
1
DIGITAL OUTPUTS MAY BECOME INVALID IN REGION
A
2
DIGITAL OUTPUTS ARE OUTPUT AS SHOWN IN REGION
B
3
DCLK1 OUTPUT MAY BECOME INVALID IN REGION
C
4
APPLICATIONS SHOULD NOT USE OUTPUT SIGNALS IN REGION C
t
1
= MINIMUM OF 2 CLI CLOCK CYCLES
*IT TAKES 4 CLI CLOCK CYCLES FROM WHEN OUTCONT GOES HIGH UNTIL VD, HD AND DIGITAL OUTPUT DATA IS VALID.
Figure 69. Reset Sequence That Must Be Applied when Changing the CLI Clock Frequency During Operation
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