- 您現在的位置：買賣IC網 > PDF目錄373971 > AD9929 (Analog Devices, Inc.) CCD Signal Processor with Precision Timing Generator PDF資料下載
參數資料
| 型號： | AD9929 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with Precision Timing Generator |
| 中文描述： | CCD信號處理器精確時序發生器 |
| 文件頁數： | 46/64頁 |
| 文件大小： | 558K |
| 代理商： | AD9929 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁當前第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
AD9929
TIMING CONTROL
ELECTRONIC SHUTTER TIMING CONTROL
CCD image exposure time is controlled through the use of the
CCD substrate clock signal (XSUBCK), which pulses the CCD
substrate to clear out accumulated charges prior to the exposure
period. The AD9929 supports three types of electronic shut-
tering: normal shutter mode, suppression shutter mode, and
high speed shutter mode. Table 34 contains the registers
required for programming of XSUBCK pulses for each mode.
Normal Shutter Mode
Figure 49 shows the VD and XSUBCK output for normal
shutter mode. The XSUBCK pulses once per line. The number
of XSUBCK pulses per field can be programmed by setting
register XSUBCKNUM (Address 0x0B). As shown in Figure 49,
the XSUBCK pulses always begin on the line after the sensor
gate, as specified by XVSGACTLINE (Mode_Reg(1)).
SUBCK Suppression Mode
Normally, the XSUBCKs begin to pulse on the line following
the last sensor gate line (VSG). With some CCDs, the first
XSUBCK following the VSG line needs to be suppressed. The
XSUBCKSUPPRESS register allows for this suppression. The
first XSUBCK following the last VSG pulse is suppressed when
XSUBCKSUPPRESS = 1, as shown in Figure 50.
High Precision Shutter Mode
The high speed shutter mode can be operated in two different
modes, known as single pulse mode and multiple pulse mode.
These modes are set up by programming the
XSUBCKNUM_HP register and XSUBCKMODE_HP register,
as described in Table 28, Table 33, and shown in Figure 52 and
Figure 54.
Rev. A | Page 46 of 64
Single Pulse Mode
In addition to the normal operating XSUBCK pulse, one addi-
tional XSUBCK pulse can be applied within the HD line while
operating in this mode. As shown in Figure 49, the location of
the additional XSUBCK pulse is adjustable by setting the
XSUBCK_HPNUM register as described in Table 33. Finer
resolution of the exposure time is possible using this mode by
adding an additional XSUBCK pulse in the line, as shown in
Figure 54.
Multiple Pulse Mode
In addition to the normal operating XSUBCK pulse, up to seven
sequential XSUBCK pulses can be applied within the same line
while operating in this mode. As shown in Figure 54, the num-
ber of additional XSUBCK pulses is selectable by setting
XSUBCKMODE_HP = 1, and the XSUBCK_HPNUM registers
as described in Table 33.
Table 33. Single and Multiple Pulse Mode
XSUBCKNUM_HP
0
XSUBCKMODE_HP
1
Single Pulse Mode
Normal Shutter
Mode Operation
Position #1
Position #2
Position #3
Position #4
Position #5
Position #6
Position #7
Multiple
Pulse Mode
Normal Shutter
Mode Operation
1 additional pulse
2 additional pulses
3 additional pulses
4 additional pulses
5 additional pulses
6 additional pulses
7 additional pulses
0
1
2
3
4
5
6
7
Table 34. XSUBCK Registers
Register Name
Bit
Width
Register Type
Reference
Counter
Range
0–2047 Number of
Pulses
Description
XSUBCKNUM
11
Control (Address 0x0B)
–
Number of XSUBCK Pulses per Field.
XSUBCKSUPPRESS 1
Control (Address 0x01)
–
0–1 Number of Pulses
Suppress First XSUBCK after Last XVSG
Line Pulse
XSUBCK Output Enable Control
(0 = Disable, 1 = Enable)
High Speed Shutter Mode Operation
High Speed Shutter XSUBCLK
Position/Number
XSUBCLK1 1st Toggle Position
XSUBCLK1 2nd Toggle Position
XSUBCLK2 1st Toggle Position
XSUBCLK2 2nd Toggle Position
(0 = XSUBCK1, 1 = XSUBCK2)
XSUBCK_EN
XSUBCKMODE_HP 1
1
Control (Address 0x0B)
Control (Address 0x01)
–
–
–
–
XSUBCKNUM_HP
3
Control (Address 0x0B)
–
0–7 Number of Pulses
XSUBCK1TOG1
XSUBCK1TOG2
XSUBCK2TOG1
XSUBCK2TOG2
XSUBCKSEL
9
9
9
9
1
System_Reg(14)
System_Reg(14)
System_Reg(15)
System_Reg(15)
Mode_Reg(2)
OL Counter
OL Counter
OL Counter
OL Counter
0–511 Pixel Location
0–511 Pixel Location
0–511 Pixel Location
0–511 Pixel Location
–
–
相關PDF資料 |
PDF描述 |
|---|---|
| AD9937 | CCD Signal Processor with Precision Timing⑩ Generator |
| AD9937KCP | CCD Signal Processor with Precision Timing⑩ Generator |
| AD9937KCPRL | TVPS00RF-25-35PB W/ PC CONTACT |
| AD9942 | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| AD9942BBCZ | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9929BBCZ | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3V 64-Pin CSP-BGA 制造商:Analog Devices 功能描述:IC 12-BIT SIGNAL PROCESSOR |
| AD9929BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9937 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor with Precision Timing⑩ Generator |
| AD9937BCPZ-24 | 制造商:Analog Devices 功能描述: |
| AD9937BCPZ-27 | 功能描述:IC CCD SIGNAL PROC/GEN 制造商:analog devices inc. 系列:* 零件狀態:上次購買時間 標準包裝:1 |
發布緊急采購，3分鐘左右您將得到回復。