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參數資料

型號：	AD9929
廠商：	Analog Devices, Inc.
英文描述：	CCD Signal Processor with Precision Timing Generator
中文描述：	CCD信號處理器精確時序發生器
文件頁數：	29/64頁
文件大小：	558K
代理商：	AD9929

AD9929

HORIZONTAL CLAMPING AND BLANKING

The AD9929’s horizontal clamping and blanking pulses are

programmable to suit a variety of applications. As with the

vertical timing generation, individual sequences are defined for

each signal, which are then organized into multiple regions

during image readout. This allows the dark pixel clamping and

blanking patterns to be changed at each stage of the readout, in

order to accommodate different image transfer timing and high

speed line shifts.

Rev. A | Page 29 of 64

CONTROLLING CLPOB CLAMP PULSE TIMING

The AFE horizontal CLPOB pulse is generated based on the

12-bit gray code counter. Once the length of the 12-bit gray

code counter is set using the HDLEN register (Sys_Reg(12)),

the CLPTOG1 and CLPTOG2 registers (Sys_Reg(15 and 16))

can be used to place the CLPOB pulse location, as shown in

Figure 25. Table 19 lists all CLPOB registers that are used to

configure and control the placement and output of the

CLPOB pulse.

The length of the last HD line is set using the HDLASTLEN

asserted when the last HD length set by HDLASTLEN is shorter

than the regular HD length set by HDLEN. Figure 24 shows

how no CLPOB pulse is applied when the last HD length set by

HDLASTLEN is longer than the regular HD length. Note that

the CLPOB pulse is applied in the last line only when

HDLASTLEN = HDLEN.

CLPOB

LAST LINE

Figure 23. Last HD Shorter than Regular HD

CLPOB

LAST LINE

Figure 24. Last HD Longer than Regular HD

Table 19. CLPOB Registers

Name

CLPOB_CONT

CLPOB_MODE 1

Bit

Width

Control (0x01)

Counter

Reference

–

Range

Description

CLPOB Control (0=CLPOB off, 1 =CLPOB On)

CLPOB CCD Region Control

(0 = Enable CLPENx Register Settings, 1 = Disable

CLPENx Register Settings)

CLPTOG1

Sys_Reg (15)

0 to 4095 pixel

locations

0 to 4095 pixel

locations

CLPOB Toggle Position 1 (Gray Code Number)

CLPTOG2

Sys_Reg

(15 and 16)

Mode_Reg (2)

CLPOB Toggle Position 2 (Gray Code Number)

CLPEN0

CLPEN1

CLPEN2

CLPEN3

CLPEN4

–

CLPOB Control for CCD Region 0