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參數資料
| 型號： | AD9929 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with Precision Timing Generator |
| 中文描述： | CCD信號處理器精確時序發生器 |
| 文件頁數： | 33/64頁 |
| 文件大小： | 558K |
| 代理商： | AD9929 |
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AD9929
VGATE MASKING OF XV1 TO XV4 AND CLPOB OUTPUTS
During slave mode operation, the SYNC/VGATE Pin 45 is
configured as an input for an external VGATE signal. While
operating in this mode, the external VGATE signal can be used
to mask the XV1 to XV4 and CLPOB outputs. There are two
options available for masking the XV1 to XV4 and CLPOB
outputs. These options are determined by the setting of the
MSHUT/VGATE_EN register located at Control Address 0x01.
Examples of these two options are shown in Figure 30 and
Figure 31. Figure 30 shows MSHUT/VGATE_EN = 0. In this
example, the VGATE signal is internally latched on the falling
VD
Rev. A | Page 33 of 64
edge of HD, resulting with the XV1 to XV4 and CLPOB outputs
being masked when the internally latched VGATE signal is
high.
Figure 31 shows MSHUT/VGATE_EN = 1. In this example, the
preprogrammed MSHUT signal blocks the VGATE input from
masking XV1 to XV4 and CLPOB outputs while MSHUT is low.
The internally latched VGATE signal only masks XV1 to XV4
and CLPOB when MSHUT is high, while operating in this
mode.
HD
VGATE
(PIN #45)
VGATE
(INTERNAL)
XV1–XV4
CLPOB
XV1–XV4 AND CLPOB MASKED
XV1–XV4 AND CLPOB MASKED
0
Figure 30. Example of VGATE Input Masking V1 to V4 and CLPOB Outputs with MSHUT/VGATE_EN = 0
VD
HD
VGATE
(PIN #45)
VGATE
XV1–XV4
(INTERNAL)
CLPOB
MSHUT
XV1–XV4 AND CLPOB MASKED
0
Figure 31. Example of VGATE Input Masking V1to V4 and CLPOB Outputs with MSHUT/VGATE_EN = 1
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