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參數資料
| 型號： | AD9929 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with Precision Timing Generator |
| 中文描述： | CCD信號處理器精確時序發生器 |
| 文件頁數： | 3/64頁 |
| 文件大小： | 558K |
| 代理商： | AD9929 |
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AD9929
SPECIFICATIONS
Table 1.
Parameter
TEMPERATURE RANGE
Operating
Storage
POWER SUPPLY VOLTAGE
AVDD (AFE Analog Supply)
TCVDD (Timing Core Analog Supply)
RGVDD (RG Driver)
HVDD (H1 to H2 Drivers)
DRVDD (Data Output Drivers)
DVDD (Digital)
VERTICAL DRIVER SUPPLY VOLTAGE
VDD (Vertical Driver Input Logic Supply)
VH1, VH2 (Vertical Driver High Supply)
VM1, VM2 (Vertical Driver Mid Supply)
VL (Vertical Driver Low Supply for 3 Level and 2 Level)
AFETG POWER DISSIPATION
36 MHz, Typ Supply Levels, 100 pF H1 to H2 Loading
Power from HVDD Only
1
Power-down Mode (AFE and Digital in Standby Operation)
VERTICAL DRIVER POWER DISSIPATION
2
(6000 pF V1 to V4 Loading, 1000 pF SUBCK Loading)
Power from VDD
Power from VH1
Power from VH2
Power from VL
MAXIMUM CLOCK RATE (CLI) AD9929
Rev. A | Page 3 of 64
Min
25
65
2.7
2.7
2.7
2.7
2.7
2.7
2.7
11.5
1.0
9.0
36
Typ
3.0
3.0
3.0
3.0
3.0
3.0
3.0
15.0
0.0
7.5
180
36
1
<1.0
23.0
15.0
42.0
Max
+85
+150
3.6
3.6
3.6
3.6
3.6
3.6
3.6
16.0
1.0
5.0
Unit
°C
°C
V
V
V
V
V
V
V
V
V
V
mW
mW
mW
mW
mW
mW
mW
MHz
1
The total power dissipated by the HVDD supply may be approximated by using the equation:
Total HVDD Power
= [
C
LOAD
×
HVDD
×
Pixel Frequency
] ×
HVDD
×
Number of H-Outputs Used.
Actual HVDD power may be slightly different than the calculated value because of the stray capacitance inherent in the PCB layout/routing.
2
Vertical driver loads used when characterizing power consumption. Note: actual power depends on the V1 to V4 timing and number of SUBCKs.
V1, V2, V3, V4
SUBCK
0
6000 pF
1000 pF
500mV TYP
RESET
TRANSIENT
100mV MAX
OPTICAL
BLACK PIXEL
1V MAX
INPUT
SIGNAL RANGE
INPUT SIGNAL CHARACTERISTICS DEFINED AS FOLLOWS:
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