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參數資料
型號: AD9929
廠商: Analog Devices, Inc.
英文描述: CCD Signal Processor with Precision Timing Generator
中文描述: CCD信號處理器精確時序發生器
文件頁數: 5/64頁
文件大小: 558K
代理商: AD9929
AD9929
TIMING SPECIFICATIONS
Table 4. C
L
= 20 pF, AVDD = DVDD = DRVDD = 3.0 V, f
CLI
= 36 MHz, unless otherwise noted.
Parameter
MASTER CLOCK, CLI
CLI Clock Period
CLI High/Low Pulse Width
Delay from CLI Rising Edge to Internal Pixel Position 0
AFE CLAMP PULSES
1
CLPOB Pulse Width
AFE SAMPLE LOCATION
1
(See Figure 17)
SHP Sample Edge to SHD Sample Edge
DATA OUTPUTS
Output Delay from DCLK1 Rising Edge (See Figure 19)
Pipeline Delay from SHP/SHD Sampling (See Figure 70)
SERIAL INTERFACE (See Figure 10 and Figure 11)
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
Rev. A | Page 5 of 64
Symbol
t
CONV
t
CLIDLY
T
S1
t
OD
t
DV
f
SCLK
t
LS
t
LH
t
DS
t
DH
t
OD
Min
27.8
4
20
10
10
10
10
10
10
Typ
13.9
6
10
25
9
Max
9
Unit
ns
ns
ns
Pixels
Pixels
ns
Cycles
MHz
ns
ns
ns
ns
ns
1
Parameter is programmable.
VERTICAL DRIVER SPECIFICATIONS
Table 5. V1 to V4 load = no load, SUBCK load = no load, VDD = 3.0 V, VL = 7.5 V, VH1 = VH2 = +15.0 V, VM1 = VM2 = GND,
f
CLI
= 36 MHz, unless otherwise noted.
Parameter
Symbol
LOGIC INPUTS
High Level Input Voltage
V
IH
Low Level Input Voltage
V
IL
Propagation Delays, Rise/Fall Times and Output Currents
V1 and V3 Outputs (See Figure 43)
Delay Times
VL to VM1
t
PLM1
VM1 to VH1
t
PMH
VH1 to VM1
t
PHM
VM1 to VL
t
PML1
Rise Times
VL to VM1
t
R1
VM1 to VH1
t
R2
Fall Times
VH1 to VM1
t
F1
VM1 to VL
t
F2
Output Currents
V1 or V3 @ VL = 7.25 V
V1 or V3 @ VM1 = 0.25 V
V1 or V3 @ VM1 = +0.25 V
V1 or V3 @ VH1 = +14.75 V
Min
0.8 (VDD)
0
Typ
0.3 (VDD)
100
100
50
50
500
500
500
500
10.0
5.0
5.0
7.2
Max
VDD
V
Unit
V
ns
ns
ns
ns
ns
ns
ns
ns
mA
mA
mA
mA
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