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參數資料
型號: AD9929
廠商: Analog Devices, Inc.
英文描述: CCD Signal Processor with Precision Timing Generator
中文描述: CCD信號處理器精確時序發生器
文件頁數: 22/64頁
文件大小: 558K
代理商: AD9929
AD9929
ANALOG FRONT END DESCRIPTION AND
OPERATION
The AD9929 AFE signal processing chain is shown in Figure 13.
Each processing step is essential in achieving a high quality
image from the raw CCD pixel data. Registers for the AD9929
AFE section are listed in Table 14.
Table 14. AFE Registers
Register
Name
Width
Register Type
VGAGAIN
10
Control (Address 0x0E)
Rev. A | Page 22 of 64
Bit
Description
VGA Gain
Black Clamp
Level
AFE Standby
REFBLACK
6
Control (Address 0x04)
AFESTBY
1
Control (Address 0x05)
DC Restore
To reduce the large dc offset of the CCD output signal, a dc-
restore circuit is used with an external 0.1 μF series coupling
capacitor. This restores the dc level of the CCD signal to
approximately 1.5 V, to be compatible with the 3 V analog
supply of the AD9929.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the
video information and reject low frequency noise. The timing
shown in Figure 16 illustrates how the two internally generated
CDS clocks, SHP and SHD, are used to sample the reference and
data levels, respectively, of the CCD signal. The placement of the
SHP and SHD sampling edges is determined by the setting of
the SHPLOC (Address 0x02) and SHDLOC (Address 0x02)
registers. Placement of these two clock edges is critical in
achieving the best performance from the CCD.
6dB TO 40dB
CCDIN
DIGITAL
FILTER
CLPOB
DC RESTORE
OPTICAL BLACK
CLAMP
ADC
VGA
8-BIT
DAC
CLAMP LEVEL
REGISTER
VGA GAIN
REGISTER
10
CDS
INTERNAL
V
REF
2V FULL
SCALE
12
PRECISION
TIMING
GENERATION
V-H
TIMING
GENERATION
SHPSHD
1.5V
OUTPUT
DATA
LATCH
REFT
REFB
DOUT
PHASE
SHP
SHD
DOUT
PHASE
CLPOB
1.0V
2.0V
DOUT
8
1.0
μ
F
1.0
μ
F
0.1
μ
F
0
Figure 13. AFE Block Diagram
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相關代理商/技術參數
參數描述
AD9929BBCZ 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3V 64-Pin CSP-BGA 制造商:Analog Devices 功能描述:IC 12-BIT SIGNAL PROCESSOR
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