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參數資料
| 型號： | AD9929 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with Precision Timing Generator |
| 中文描述： | CCD信號處理器精確時序發生器 |
| 文件頁數： | 48/64頁 |
| 文件大小： | 558K |
| 代理商： | AD9929 |
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AD9929
VSG TIMING
The VSG Timing is controlled using the registers in Table 35.
Two unique preprogrammed VSG pulses can be configured
using the XVSGTOG_x (x = 0, 1) registers. As shown in
Figure 55, the period of the VSG pulse is set by programming
the XVSGLEN_x registers. The XVSGSELx (x = 1, 2) can then
be used to select the XVSGTOG_0 or XVSGTOG_1 pulse.
Figure 55 also shows an example of the XVSG pulse being
output in the fourth line by setting the XVSGACTLINE = 3.
The XVSG pulses references the 13-bit fixed ST counter, which
starts counting from the line set in the XVSGACTLINE register.
The 13-bit counter allows for overlapping of the XVSG pulse
into the next line if needed.
Rev. A | Page 48 of 64
Figure 53 describes the XVSG1 and XVSG2 MUX operation
using the XVSGSELx registers.
XVSGTOG_0
XVSGTOG_1
XVSGSEL1
XVSG1
XVSGTOG_0
XVSGTOG_1
XVSGSEL2
XVSG2
(APPLIED TO XV1)
(APPLIED TO XV3)
0
Figure 53. XVSGSELx Registers
HD
XSUBCK
1
2
3
9-BIT
OL-COUNTER
0
Figure 54. Electronic Shutter Timing Example with XSUBCKMODE_HP = 1 and XSUBCKNUM_HP = 3.
Table 35. VSG Registers
Register
Name
XVSGMASK
XVSG_EN
XVSGTOG_0
XVSGTOG_1
XVSGLEN_0
XVSGLEN_1
Bit
Width
6
1
11
11
8
8
Register Type
Control (Address 0x0A)
Control (Address 0x0B)
Sys_Reg(13)
Sys_Reg(13)
Sys_Reg(14)
Control (Address 0x0F)
Reference
Counter
–
–
ST
ST
ST
ST
Range
Description
VSG Mask Control
(00 = XVSG1 Masked, XVSG2 Masked)
(02 = XVSG1 Not Masked, XVSG2 Masked)
(08 = XVSG1 Masked, XVSG2 Not Masked)
(0A= XVSG1 Not Masked, XVSG2 Not Masked)
XVSG Output Enable Control (0 = Disable
XVSG Outputs, 1 = Enable XVSG Outputs)
XVSGTOG_0 Toggle Position
XVSG TOG_1 Toggle Position
XVSGTOG_0 Pulse Width
XVSGTOG_1 Pulse Width
XVSG1 Selector
(0 = XVSGTOG_0 Applied on XVSG1,
1 = XVSGTOG_1 Applied on XVSG1)
XVSG2 Selector
(0 = XVSGTOG_0 Applied on XVSG2,
1 = XVSGTOG_1 Applied on XVSG2 )
VSG Active Line
–
High/Low
0–8191 Pixels
0–8191 Pixels
0–255 Pixels
0–255 Pixels
High/Low
XVSGSEL1
1
Mode_Reg(1)
–
XVSGSEL2
1
Mode_Reg(1)
–
High/Low
XVSGACTLINE
7
Mode_Reg(1)
0–128 Lines
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