- 您現在的位置：買賣IC網 > PDF目錄373971 > AD9929 (Analog Devices, Inc.) CCD Signal Processor with Precision Timing Generator PDF資料下載
參數資料
| 型號： | AD9929 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with Precision Timing Generator |
| 中文描述： | CCD信號處理器精確時序發生器 |
| 文件頁數： | 34/64頁 |
| 文件大小： | 558K |
| 代理商： | AD9929 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
AD9929
VERTICAL TIMING GENERATION
The AD9929 provides a very flexible solution for generating
vertical CCD timing and can support multiple CCDs and
different system architectures. The 4-phase vertical transfer
clocks XV1 to XV4 are used to shift each line of pixels into the
horizontal output register of the CCD. The AD9929 vertical
outputs can be individually programmed into four different
vertical pulse patterns identified as VTP0, VTP1, VTP2, and
VTP3. Each vertical pulse pattern is a unique set of precon-
figured XV1 to XV4 sequences. Once the vertical patterns have
been configured using the registers shown in Table 24, pointer
registers are used to select in which region of the CCD a
particular vertical pattern is output. The pointer registers are
described in Table 22.
Rev. A | Page 34 of 64
Up to five unique CCD regions may be specified. Finally, the
readout of the entire field is constructed by combining one or
more of the individual regions sequentially. With up to five
regions available, different steps of the readout such as high
speed line shifts and vertical image transfer can be supported.
CREATING VERTICAL SEQUENCES
Figure 32 through Figure 34 provide an overview of how the
vertical timing is generated in four basic steps.
Step 1
: Create the individual pulses for patterns VTP0, VTP1,
VTP2, and VTP3 (see
Figure 32
).
The registers shown in Table 22 are used to generate the
individual vertical timing pulses, as shown in Figure 32.
The VTPLENx determines the number of pixels between pulse
repetitions. The start polarity (XVxSTARTPOLx) sets the
starting polarity of the vertical sequence and can be program-
med high or low. The first toggle position (XVxTOG1POSx)
and second toggle position (XVxTOG2POSx) are the pixel
locations within the line where the pulse transitions.
Step 2
: Create the individual vertical sequences (see Figure 33).
Create the individual vertical sequences by assigning pulse
repetitions to patterns VTP0, VTP1, VTP2, and VTP3 using the
VTPREPx registers as shown in Table 25. The number of repeti-
tions (VTPREPx) determines the number of pulse repetitions
desired within a single line. Programming 1 for VTPREPx gives
a single pulse, and setting to 0 provides a fixed dc output based
on the start polarity value. Figure 33 shows an example of a
VTPx sequence of two VTPx patterns by setting VTPREPx = 2.
Step 3
: Output Vertical Sequences into CCD Regions (see
Figure 34
).
The AD9929 arranges individual sequences into CCD regions
through the use of sequence pointers (VTPSEQPTRx) and
vertical transfer pattern select (VTPSELx) registers, as described
in Table 23. The VTPSEQPTRx registers are used to point to a
desired VTPSELx register whose value determines what VTPx
pattern is output on the XV1 to XV4 signals. For example, if
VTPSEQPTR0 = 1 and VTPSEL1 = 2, the VTP2 pulse pattern
would output while operating in Region 0 of the CCD.
Step 4
: Combining CCD Regions (see Figure 34
).
Build the entire field readout by combining multiple regions by
using mode registers SCP0, SCP1, SCP2, SCP3, and SCP4.
The individual CCD regions are combined into a complete field
readout by using sequence change position (SCPx) pointers as
described in Table 23. Figure 34 shows how each field is divided
into multiple regions. This allows the user to change vertical
timing during various stages of the image readout. The boun-
daries of each region are defined by the sequence change
position (SCP). Each SCP is a 8-bit value representing the line
number boundary region. A total of four SCPs allow up to five
different region areas in the field to be defined. The first SCP0 is
always hard-coded to line 0, and the remaining four SCPs are
register programmable.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9937 | CCD Signal Processor with Precision Timing⑩ Generator |
| AD9937KCP | CCD Signal Processor with Precision Timing⑩ Generator |
| AD9937KCPRL | TVPS00RF-25-35PB W/ PC CONTACT |
| AD9942 | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| AD9942BBCZ | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9929BBCZ | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3V 64-Pin CSP-BGA 制造商:Analog Devices 功能描述:IC 12-BIT SIGNAL PROCESSOR |
| AD9929BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9937 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor with Precision Timing⑩ Generator |
| AD9937BCPZ-24 | 制造商:Analog Devices 功能描述: |
| AD9937BCPZ-27 | 功能描述:IC CCD SIGNAL PROC/GEN 制造商:analog devices inc. 系列:* 零件狀態:上次購買時間 標準包裝:1 |
發布緊急采購，3分鐘左右您將得到回復。