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參數(shù)資料
| 型號(hào)： | AD9929 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with Precision Timing Generator |
| 中文描述： | CCD信號(hào)處理器精確時(shí)序發(fā)生器 |
| 文件頁(yè)數(shù)： | 24/64頁(yè) |
| 文件大小： | 558K |
| 代理商： | AD9929 |
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AD9929
As shown in Figure 17, the H2 output is the inverse of H1. The
internal propagation delay resulting from the signal inversion is
less than 1 ns, which is significantly less than the typical rise
Rev. A | Page 24 of 64
time driving the CCD load. This results in a H1/H2 crossover
voltage at approximately 50% of the output swing. The
crossover voltage is not programmable.
NOTES
1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (
t
CLIDLY
= 6ns TYP).
P[0]
P[48] = P[0]
P[12]
P[24]
P[36]
1 PIXEL
PERIOD
CLI
t
CLIDLY
POSITION
0
Figure 15. High Speed Clock Resolution from CLI Master Clock Input
3
H1
H2
CCD
SIGNAL
RG
PROGRAMMABLE CLOCK POSITIONS
1. RG RISING EDGE (FIXED EDGE AT 000000)
2. RG FALLING EDGE (RGNEGLOC (ADDRESS 0x03))
3. SHP SAMPLE LOCATION (SHPLOC (ADDRESS 0x02))
4. SHD SAMPLE LOCATION (SHDLOC (ADDRESS 0x02))
5. H1 RISING EDGE LOCATION (H1POSLOC (ADDRESS 0x03))
6. H1 NEGATIVE EDGE LOCATION (FIXED AT (H1POSLOC + 24 STEPS))
7. H2 IS ALWAYS THE INVERSE OF H1
4
1
2
5
6
CDS
(INTERNAL)
0
Figure 16. High Speed Clock Programmable Locations
Table 15. RG, H1, SHP, SHD, DCLK, and DOUTPHASE Timing Parameters
Register Name
Bit Width
Register Type
RGNEGLOC
1
6b
Control (Address 0x03)
H1POSLOC
1
6b
Control (Address 0x03)
SHPLOC
1
6b
Control (Address 0x02)
SHDLOC
1
6b
Control (Address 0x02)
DOUTPHASE
1
6b
Control (Address 0x02)
DCLKPHASE
6b
Control (Address 0x02)
Range
0 to 47 Edge Location
0 to 47 Edge Location
0 to 47 Edge Location
0 to 47 Edge Location
0 to 47 Edge Location
0 to 47 Edge Location
Description
Falling Edge Location for RG
Positive Edge Location for H1
Sample Location for SHP
Sample Location for SHD
Phase Location of Data Output [9:0]
Positive Edge of DCLK 1
1
The two MSB bits are used to select the quadrant
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