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參數(shù)資料
型號(hào)： AD9929
廠商： Analog Devices, Inc.
英文描述： CCD Signal Processor with Precision Timing Generator
中文描述： CCD信號(hào)處理器精確時(shí)序發(fā)生器
文件頁數(shù)： 37/64頁
文件大?。?/td> 558K
代理商： AD9929
AD9929
Table 22. XV1 to XV4 Registers to Configure XXV1 to XXV4 Pulses for each VTP Pattern
Bit
Width
Register Type
VTPLEN0
9
Sys_Reg(1)
Rev. A | Page 37 of 64
Register Name
Reference
Counter
V Counter
Range
Description
Length between Repetitions
XV1 Starting Polarity for VTP0
(0 = Low, 1 = High)
XV2 Starting Polarity for VTP0
(0 = Low, 1 = High)
XV3 Starting Polarity for VTP0
(0 = Low, 1 = High)
XV4 Starting Polarity for VTP0
(0 = Low, 1 = High)
XV1 Toggle Position 1 for VTP0
XV1 Toggle Position 2 for VTP0
XV2 Toggle Position 1 for VTP0
XV2 Toggle Position 2 for VTP0
XV3 Toggle Position 1 for VTP0
XV3 Toggle Position 2 for VTP0
XV3 Toggle Position 1 for VTP0
XV3 Toggle Position 2 for VTP0
Length between Repetitions
XV1 Starting Polarity for VTP1
(0 = Low, 1 = High)
XV2 Starting Polarity for VTP1
(0 = Low, 1 = High)
XV3 Starting Polarity for VTP1
(0 = Low, 1 = High)
XV4 Starting Polarity for VTP1
(0 = Low, 1 = High)
XV1 Toggle Position 1 for VTP1
XV1 Toggle Position 2 for VTP1
XV2 Toggle Position 1 for VTP1
XV2 Toggle Position 2 for VTP1
XV3 Toggle Position 1 for VTP1
XV3 Toggle Position 2 for VTP1
XV3 Toggle Position 1 for VTP1
XV3 Toggle Position 2 for VTP1
Length between Repetitions
XV1 Starting Polarity for VTP2
(0 = Low, 1 = High)
XV2 Starting Polarity for VTP2
(0 = Low, 1 = High)
XV3 Starting Polarity for VTP2
(0 = Low, 1 = High)
XV4 Starting Polarity for VTP2
(0 = Low, 1 = High)
XV1 Toggle Position 1 for VTP2
XV1 Toggle Position 1 for VTP2
XV1 Toggle Position 2 for VTP2
XV2 Toggle Position 1 for VTP2
XV3 Toggle Position 1 for VTP2
XV3 Toggle Position 2 for VTP2
XV3 Toggle Position 1 for VTP2
XV3 Toggle Position 2 for VTP2
VTP
Pattern
0–511
High/Low
XV1STARTPOL0
1
Sys_Reg(1)
XV2STARTPOL0
1
Sys_Reg(1)
High/Low
XV3STARTPOL0
1
Sys_Reg(1)
High/Low
XV4STARTPOL0
1
Sys_Reg(1)
High/Low
XV1TOG1POS0
XV1TOG2POS0
XV2TOG1POS0
XV2TOG2POS0
XV3TOG1POS0
XV3TOG2POS0
XV4TOG1POS0
XV4TOG2POS0
VTPLEN1
9
9
9
9
9
9
9
9
9
Sys_Reg(1)
Sys_Reg(1)
Sys_Reg(1 & 2)
Sys_Reg(2)
Sys_Reg(2)
Sys_Reg(2 & 3)
Sys_Reg(3)
Sys_Reg(3)
Sys_Reg(3)
V Counter
V Counter
V Counter
V Counter
V Counter
V Counter
V Counter
V Counter
V Counter
0–511
0–511
0–511
0–511
0–511
0–511
0–511
0–511
0–512
High/Low
VTP0
XV1STARTPOL1
1
Sys_Reg(3)
XV2STARTPOL1
1
Sys_Reg(3)
High/Low
XV3STARTPOL1
1
Sys_Reg(4)
High/Low
XV4STARTPOL1
1
Sys_Reg(4)
High/Low
XV1TOG1POS1
XV1TOG2POS1
XV2TOG1POS1
XV2TOG2POS1
XV3TOG1POS1
XV3TOG2POS1
XV4TOG1POS1
XV4TOG2POS1
VTPLEN2
9
9
9
9
9
9
9
9
9
Sys_Reg(4)
Sys_Reg(4)
Sys_Reg(4
Sys_Reg(4 & 5)
Sys_Reg(5)
Sys_Reg(5)
Sys_Reg(5 & 6)
Sys_Reg(6)
Sys_Reg(6)
V Counter
V Counter
V Counter
V Counter
V Counter
V Counter
V Counter
V Counter
V Counter
0–511
0–511
0–511
0–511
0–511
0–511
0–511
0–511
0–512
High/Low
VTP1
XV1STARTPOL2
1
Sys_Reg(6)
XV2STARTPOL2
1
Sys_Reg(6)
High/Low
XV3STARTPOL2
1
Sys_Reg(6)
High/Low
XV4STARTPOL2
1
Sys_Reg(6)
High/Low
XV1TOG1POS2
XV1TOG1POS2
XV1TOG2POS2
XV2TOG1POS2
XV3TOG1POS2
XV3TOG2POS2
XV4TOG1POS2
XV4TOG2POS2
9
9
9
9
9
9
9
9
Sys_Reg(6)
Sys_Reg(7)
Sys_Reg(7)
Sys_Reg(7)
Sys_Reg(7 & 8)
Sys_Reg(8)
Sys_Reg(8)
Sys_Reg(8)
V Counter
V Counter
V Counter
V Counter
V Counter
V Counter
V Counter
V Counter
0–511
0–511
0–511
0–511
0–511
0–511
0–511
0–511
VTP2
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