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參數資料
| 型號： | AD9929 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with Precision Timing Generator |
| 中文描述： | CCD信號處理器精確時序發生器 |
| 文件頁數： | 28/64頁 |
| 文件大小： | 558K |
| 代理商： | AD9929 |
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AD9929
HORIZONTAL AND VERTICAL SYNCHRONOUS TIMING
The HD and VD output pulses are programmable using the
registers listed in Table 18. The HD output is asserted low at the
start of the horizontal line shift. The VD output is asserted low
at the start of each line. As shown in Figure 22, the 11-bit VD
counter is used to count the number of lines set by the VDLEN
register. The 12-bit HD counter is used to count the number of
pixels in each line set by the HDLEN register. For example, if
the CCD array size is 2000 lines by 2100 pixels per line,
VDLEN = 2000 and HDLEN = 0xC28. The HDLEN register
sets HL as a reference for the rising edge of the HD pulse.
Rev. A | Page 28 of 64
SPECIAL NOTE ABOUT THE HDLEN REGISTER
The 12-bit HD counter value must be programmed using a gray
code number. There is also a 4-clock cycle, set up period that
must be considered when determining the HDLEN register
value, as shown in Figure 22. As a result of the 4-clock cycle,
setup period, the value of HDLEN is always equal to the actual
number of pixels per line minus 4. For example, if there are
2100 pixels per line, HDLEN equals (2100 – 4) = 2096. The gray
code value of 2096 is 0xC28, which is what would be program-
med in the HDLEN register.
Table 18. HD and VD Registers
Register Name
HDLEN
1
HLEN
HDRISE
HDLASTLEN
1
VDLEN
VDRISE
Bit
Width
12
10
10
12
11
4
Register Type
Sys_Reg(12)
Sys_Reg(12)
Sys_Reg(16)
Mode_Reg(1)
Mode_Reg(1)
Sys_Reg(16)
Reference
Counter
–
–
HL
HD
–
VD
Range
0–4095 Pixels
0–1023 Pixels
0–1023 Pixels
0–4095 Pixels
0–2047 Lines
0–15 Lines
Description
12-Bit Gray Code Counter Value
10-Bit HL-Counter Value
HD Rise Position
HD Last Line Length
VD Counter Value
VD Rise Position
1
Register value must be a gray code number (see Gray Code Registers section).
VD
HDLASTLEN
VDLEN
000
001
002
11-BIT
VD COUNTER
12-BIT
GRAY COUNTER
+ SET- UP
S
HDLEN
10-BIT
HL COUNTER
HD
2
NOTES
1. THE SET-UP DELAY IS 4 CLI CYCLES. THE ACTUAL LENGTH OF ONE LINE IS 4 MORE CYCLES
THAN VALUE SET IN HDLEN AND HDLASTLEN DUE TO SET-UP DELAY.
2. VDRISE REFERENCES THE 11-BIT VD-COUNTER.
3. HDRISE REFERENCES THE 10-BIT HL-CONTER.
1
PROGRAMMABLE CLOCK POSITIONS
1. HDRISE (SYS_REG(16))
2. VDRISE (SYS_REG(16))
N_ 2048
HLEN
LINE LENGTH =
HDLEN + 4
0
Figure 22. VD and HD Horizontal Timing
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