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參數(shù)資料
型號(hào)： AD9929
廠商： Analog Devices, Inc.
英文描述： CCD Signal Processor with Precision Timing Generator
中文描述： CCD信號(hào)處理器精確時(shí)序發(fā)生器
文件頁(yè)數(shù)： 40/64頁(yè)
文件大小： 558K
代理商： AD9929
AD9929
SPECIAL VERTICAL TIMING (SPATS)
The AD9929 provides additional special vertical timing gen-
eration (SPATs), which is applied in the same line as the VSG
pulse. The SPAT timing allows for an additional vertical output
pulse in the VSG line. The additional vertical output pulse can
be applied to either XV1, XV2, XV3 or XV4, according to the
value of the SPATLOGIC register. Table 26 lists the registers
used to generate the SPATs, and Table 27 describes the
SPATLOGIC settings and operation.
Rev. A | Page 40 of 64
Figure 39 and Figure 40 show AND and OR SPAT pulse
examples using four SPAT toggle positions. As shown in these
figures, the internal SPAT timing for the AND case initially
starts high and then goes low at the first XVxSPAT_TOG1
position. In the OR case, the internal SPAT timing initially starts
low and then toggles high at the first XVxSPAT_TOG1 position.
This provides the ability to output the second vertical pulse
when the internal XVx pulse is in both high and low states. Note
that although Figure 39 and Figure 40 show four SPAT toggle
positions, two SPAT toggle positions can be applied by setting
XVxSPAT_TOG3 = XVxSPAT_TOG4 = 0x1FFF.
Table 26. HD and VD Registers
Register Name
SPAT_EN
SPATLOGIC
Bit
Width
1
4
Register Type
Control (Address 0x01)
Control (Address 0x0A)
Reference
Counter
–
–
Range (Pixels)
Description
SPAT Enable Control
(0 = SPAT Disabled, 1 = SPAT Enabled)
SPAT Logic Setting
XV1SPAT Toggle Position #1
(Mode_A Active)
XV1SPAT Toggle Position #2
(Mode_A Active)
XV1SPAT Toggle Position #3
(Mode_A Active)
XV1SPAT Toggle Position #4
(Mode_A Active)
XV2SPAT Toggle Position #1
(Mode_A Active)
XV2SPAT Toggle Position #2
(Mode_A Active)
XV2SPAT Toggle Position #3
(Mode_A Active)
XV2SPAT Toggle Position #4
(Mode_A Active)
XV3SPAT Toggle Position #1
(Mode_A Active)
XV3SPAT Toggle Position #2
(Mode_A Active)
XV3SPAT Toggle Position #3
(Mode_A Active)
XV3SPAT Toggle Position #4
(Mode_A Active)
XV4SPAT Toggle Position #1
(Mode_A Active)
XV4SPAT Toggle Position #2
(Mode_A Active)
XV4SPAT Toggle Position #3
(Mode_A Active)
XV4SPAT Toggle Position #4
(Mode_A Active)
XV1SPAT Toggle Position #1
(Mode_B Active)
XV1SPAT Toggle Position #2
(Mode_B Active)
XV1SPAT Toggle Position #3
(Mode_B Active)
XV1SPAT Toggle Position #4
(Mode_B Active)
XV1SPAT_TOG1 13
Control (Address 0x17)
ST
0–8192
XV1SPAT_TOG2 13
Control (Address 0x18)
ST
0–8192
XV1SPAT_TOG3 13
Mode_A_Reg(5)
ST
0–8192
XV1SPAT_TOG4 13
Mode_A_Reg(5)
ST
0–8192
XV2SPAT_TOG1 13
Control (Address 0x19)
ST
0–8192
XV2SPAT_TOG2 13
Control (Address 0x1A)
ST
0–8192
XV2SPAT_TOG3 13
Mode_A_Reg(5)
ST
0–8192
XV2SPAT_TOG4 13
Mode_A_Reg(5)
ST
0–8192
XV3SPAT_TOG1 13
Control (Address 0x1B)
ST
0–8192
XV3SPAT_TOG2 13
Control (Address 0x1C)
ST
0–8192
XV3SPAT_TOG3 13
Mode_A_Reg(5)
ST
0–8192
XV3SPAT_TOG4 13
Mode_A_Reg(5)
ST
0–8192
XV4SPAT_TOG1 13
Control (Address 0x1D)
ST
0–8192
XV4SPAT_TOG2 13
Control (Address 0x1E)
ST
0–8192
XV4SPAT_TOG3 13
Mode_A_Reg(5)
ST
0–8192
XV4SPAT_TOG4 13
Mode_A_Reg(5)
ST
0–8192
XV1SPAT_TOG1 13
Control (Address 0x1F)
ST
0–8192
XV1SPAT_TOG2 13
Control (Address 0x20)
ST
0–8192
XV1SPAT_TOG3 13
Mode_B_Reg(5)
ST
0–8192
XV1SPAT_TOG4 13
Mode_B_Reg(5)
ST
0–8192
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