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參數資料
| 型號： | L84225 |
| 英文描述： | L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02 |
| 中文描述： | L84225 100BaseTX/FX/10BaseT物理層設備的技術手冊，4月2日 |
| 文件頁數： | 18/118頁 |
| 文件大小： | 890K |
| 代理商： | L84225 |
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18 of 118
April, 2002
L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
The MII consists of four transmit data bits (TXD[3:0]), transmit clock
(TXCLK), transmit enable (TXEN), transmit error (TXER), four receive
data bits (RXD[3:0]), receive clock (RXCLK), carrier sense (CRS),
receive data valid (RXDV), receive data error (RXER), and collision
(COL). The transmit clock (TXCLK) is a common signal for all four
channels. All other signals are separate for each channel. The transmit
and receive clocks operate at 25 MHz in 100 Mbps mode.
On the transmit side, the TXCLK output runs continuously at 25 MHz.
When no data is to be transmitted, TXEN must be deasserted. While
TXEN is deasserted, TXER and TXD[3:0] are ignored and no data is
clocked into the device. When TXEN is asserted on the rising edge of
TXCLK, data on TXD[3:0] is clocked into the device on rising edges of
the TXCLK output clock. TXD[3:0] input data is nibble wide packet data
whose format is specified in IEEE 802.3 and shown in
Figure 3
. When
all packet data has been latched into the device, TXEN must be
deasserted on the rising edge of TXCLK.
TXER is also clocked in on rising edges of the TXCLK clock. TXER is a
transmit error signal which, when asserted, will substitute an error nibble
in place of the normal data nibble that was clocked in on the TXD[3:0]
nibble at the same time as the TXER assertion. The error nibble is the
/H/ symbol, as defined in IEEE 802.3 and shown in
Table 3
.
Since CLKIN (input clock) generates TXCLK (output clock), TXD[3:0],
TXEN, and TXER are also clocked in on the rising edges of CLKIN.
On the receive side, as long as a valid data packet is not detected, CRS
and RXDV are deasserted and RXD[3:0] is held low. When the start of
packet is detected, CRS is asserted on the falling edge of RXCLK. The
assertion of RXDV indicates that valid data is available on RXD[3:0].
Data may be externally latched using the rising edge of RXCLK. The
RXD[3:0] data has the same frame structure as the TXD[3:0] data,
specified in IEEE 802.3 and shown in
Figure 3
. When the end of packet
is detected, CRS and RXDV are deasserted, and RXD[3:0] is held low.
CRS and RXDV also stay deasserted if the channel is in Link Fail state.
RXER is a receive error output that is asserted when certain errors are
detected on a data nibble. RXER is asserted on the falling edge of
RXCLK for the duration of the RXCLK clock cycle during which the nibble
containing the error is output on RXD[3:0].
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