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參數資料
| 型號： | L84225 |
| 英文描述： | L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02 |
| 中文描述： | L84225 100BaseTX/FX/10BaseT物理層設備的技術手冊，4月2日 |
| 文件頁數： | 54/118頁 |
| 文件大?。?/td> | 890K |
| 代理商： | L84225 |
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54 of 118
April, 2002
L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
2.25.5 Frame Structure
The structure of the serial port frame is shown in
Table 8
and a timing
diagram is shown in
Figure 9
. Each serial port access cycle consists of
32 bits (or 720 bits if multiple register access is enabled and
REGAD[4:0]=11111), exclusive of idle. The first 16 bits of the serial port
cycle are always write bits and are used for addressing. The last 16/704
bits are from one/all of the 4 x 11 data registers.
The first 2 bits in
Table 8
and
Figure 9
are start bits and need to be
written as a 01 for the serial port cycle to continue. The next 2 bits are
read and write bits that determine whether the accessed data register
bits will be read or write. The next 5 bits are device addresses. The 3
most significant bits must match the values on pins PHYAD[4:2] and the
2 least significant bits select one of four channels for access. The next 5
bits are register address select bits, which select one of the eleven
registers for access. The next 2 bits are turnaround bits which are not an
actual register bits but extra time to switch MDIO from write to read if
necessary. The final 16 bits of the MI serial port cycle (or 704 bits if
multiple register access is enabled and REGAD[4:0]=11111) come from
the specific data register designated by the register address bits
REGAD[4:0].
2.25.6 Register Structure
The L84225 has eleven 16 bit registers for each channel. All eleven
registers are available for setting configuration inputs and reading status
outputs. A map of the registers is shown in
Table 9
. The eleven registers
consist of six registers that are defined by IEEE 802.3 specifications
(Registers 0-5) and five registers that are unique to the L84225
(Registers 16-20).
The structure and bit definition of the Control Register is shown in
Table 10
. This register stores various configuration inputs and its bit
definition complies with the IEEE 802.3 specifications.
The structure and bit definition of the Status Register is shown in
Table 11
. This register contains device capabilities and status output
information and its bit definition complies with the IEEE 802.3
specifications.
The structure and bit definition of the PHY ID Register 1 and PHY ID
Register 2 is shown in
Table 12
and
Table 13
, respectively. These
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相關代理商/技術參數 |
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| L84225/B1 | 制造商:LSI Corporation 功能描述: |
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| L8446-41 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
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