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April, 2002
L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
programmed to be a link detect output, these pins are asserted low
whenever the device is in the Link Pass state.
2.14.10 Link Disable
The link integrity function can be disabled by setting the link disable bit
in the MI serial port Configuration 1 register. When the link integrity
function is disabled, the device is forced into the Link Pass state,
configures itself for Half/Full Duplex based on the value of the duplex bit
in the MI serial port Control register, configures itself for 100/ 10 Mbps
operation based on the values of the speed bit in the MI serial port
Control register, and continues to transmit NLP’s or TX idle patterns,
depending on whether the device is in 10 or 100 Mbps mode.
2.15 Jabber
2.15.1 100 Mbps
The jabber function is disabled in the 100 Mbps mode.
2.15.2 10 Mbps
A jabber condition occurs when the transmit packet exceeds a
predetermined length. When jabber is detected, the TP transmit outputs
are forced to the idle state, collision is asserted, and jabber register bits
in the MI serial port Status and Channel Status Output registers are set.
2.16 Receive Polarity Correction
2.16.1 100 Mbps
No polarity detection or correction is needed in 100 Mbps mode.
2.16.2 10 Mbps
The polarity of the signal on the TP receive input is continuously
monitored. If one SOI pulse indicates incorrect polarity on the TP receive
input, the polarity is internally determined to be incorrect, and the reverse
polarity bit is set in the MI serial port Channel Status Output register.
The L84225 will automatically correct for the reverse polarity condition if
the autopolarity feature is not disabled.