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參數資料
| 型號： | L84225 |
| 英文描述： | L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02 |
| 中文描述： | L84225 100BaseTX/FX/10BaseT物理層設備的技術手冊，4月2日 |
| 文件頁數： | 81/118頁 |
| 文件大小： | 890K |
| 代理商： | L84225 |
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Application Information
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
81 of 118
April, 2002
The L84225 also offers RMII (Reduced MII) interface as a selectable
option for use with controllers (MACs) supporting RMII operation. By
holding the RMII_EN pin high, the RMII interface is enabled, cutting the
required interface signals from 16 to 6. This is a significant savings in
board interconnect for high port count systems.
For normal MII operation, the RMII_EN pin should be tied to GND. Refer
to the RMII description in Section 2 for details of the interface operation.
4.6.2 Clocks
Standard Ethernet controllers with an MII use TXCLK to clock data in on
inputs TXD[3:0]. TXCLK is specified in IEEE 802.3 and on the L84225
to be an output. The L84225 requires a 25 MHz reference frequency in
MII mode, and 50 MHz in RMII mode. This reference frequency must be
applied to the CLKIN pin. CLKIN generates TXCLK inside the L84225;
thus, data can be clocked into the L84225 on the rising edge of output
clock TXCLK or on the rising edge of input clock CLKIN.
If a nonstandard controller is used to interface to the L84225, or in
Repeater Applications, there may be a need to clock TXD[3:0] into the
L84225 on the rising edge CLKIN. Where CLKIN is used as the input
clock, TXCLK can be left open or used for another purpose.
4.6.3 MII Disable
The MII outputs can be placed in the high impedance state and inputs
disabled by setting the MII disable bit in the MI serial port Control
register. When this bit is set to the disable state, the TP and FX outputs
are both disabled and transmission is inhibited. The default value of this
bit when the device powers up or is reset is dependent on the device
address. If the device address latched into PHYAD[4:0] at reset is 11111,
it is assumed that the device is being used in applications where there
maybe more than one device sharing the MII bus, like external PHYs or
adapter cards, so the device powers up with the MII interface disabled.
If the device address latched into PHYAD[4:0] at reset is not 11111, it is
assumed that the device is being used in an application where it is the
only device on the MII bus, like hubs, so the device powers up with the
MII interface enabled.
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相關代理商/技術參數 |
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| L84225/B1 | 制造商:LSI Corporation 功能描述: |
| L8446-04 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
| L8446-06 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
| L8446-07 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
| L8446-41 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
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