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參數(shù)資料
| 型號(hào)： | L84225 |
| 英文描述： | L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02 |
| 中文描述： | L84225 100BaseTX/FX/10BaseT物理層設(shè)備的技術(shù)手冊(cè)，4月2日 |
| 文件頁(yè)數(shù)： | 6/118頁(yè) |
| 文件大小： | 890K |
| 代理商： | L84225 |
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April, 2002
L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
Controller Interface (MII & RMII)
Pin #
Pin Name
I/O
Description
87
69
50
31
TXCLK_[3:0]
O
Transmit Clock Output.
These interface outputs provide clocks to
external controllers. Transmit data from the controller on TXD,
TXEN, and TXER is clocked in on the rising edges of TXCLK and
CLKIN.
88
70
51
32
TXEN_[3:0]
I
Transmit Enable Input.
These interface inputs must be asserted
active high to allow data on TXD and TXER to be clocked in on
the rising edges of TXCLK and CLKIN.
[92:89]
[74:71]
[55:52]
[36:33]
TXD[3:0]_3
TXD[3:0]_2
TXD[3:0]_1
TXD[3:0]_0
I
Transmit Data Input.
These interface inputs contain input nibble
data to be transmitted on the TP or FX outputs and are clocked in
on rising edges of TXCLK and CLKIN. In RMII mode, only
TXD[1:0] are used.
86
68
49
30
TXER_[3:0]/
TXD4_[3:0]
I
Transmit Error Input.
These interface inputs initiate an error pat-
tern to be transmitted on the TP or FX outputs and are clocked in
on rising edges of TXCLK when TXEN is asserted.
If the channel is placed in the Bypass 4B5B Encoder mode, these
pins are reconfigured to be the fifth TXD transmit data input,
TXD4. In RMII mode, these pins are not used.
84
66
47
28
RXCLK_[3:0]
O
Receive Clock Output.
These interface outputs provide a clock to
the controller. Receive data on RXD, RXDV, and RXER is clocked
out to the controller on falling edges of RXCLK.
94
76
58
38
CRS_[3:0]
O
Carrier Sense Output.
These interface outputs are asserted
active high when valid data is detected on the receive TP or FX
inputs and is clocked out on the falling edge of RXCLK.
83
65
46
27
RXDV_[3:0]
O
Receive Data Valid Output.
These interface outputs are asserted
active high when valid decoded data is present on the RXD out-
puts and is clocked out on falling edges of RXCLK. In RMII mode,
these pins are not used.
[79:82]
[61:64]
[42:45]
[23:26]
RXD[3:0]_3
RXD[3:0]_2
RXD[3:0]_1
RXD[3:0]_0
O
Receive Data Output.
These interface outputs contain recovered
nibble data from the TP or FX inputs and are clocked out on the
falling edges of RXCLK. In RMII mode, only RXD[1:0] are used.
Pin Description (Cont.)
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