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參數資料
| 型號： | Z550 |
| 元件分類： | 通信、網絡模塊及開發工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數據通信 |
| 文件頁數： | 10/30頁 |
| 文件大小： | 581K |
| 代理商： | Z550 |
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Z550 UART
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10
Oki Semiconductor
Modem Control Register
The Modem Control Register (MCR) controls the interface with a modem or data set as shown in
and the following table. The MCR can be written and read. The RTS and DTR outputs are directly con-
trolled by bits in this register. A high input asserts a low (true) at the output pins.
Figure 6
Figure 6. Modem Control Register
FCR(3)
DMA Mode Select. This bit controls the method of DMA signaling that will be used. If FCR(3)=1, the part will
operate in Mode 1. It will be in Mode 0 if FCR(3)=0. These modes are only valid if FCR(0)=1. It directly affects
the operation of the RXRDY and TXRDY outputs.
FCR(4)-FCR(5) These bits are not used.
FCR(6)-FCR(7) Rx FIFO Interrupt Trigger Level. These two bits are used to set the trigger level for the RCVR FIFO interrupt.
Modem Control Register Description
MCR Bit(s)
Bit Description
MCR(0):
When MCR(0) is set high, the DTR output is forced low. When MCR(0) is reset low, the DTR output
is forced high.
MCR(1):
When MCR(1) is set high, the RTS output is forced low. When MCR(1) is reset low, the RTS output
is forced high.
MCR(2):
When MCR(2) is set high, the OUT1 output is forced low. When MCR(2) is reset low, the OUT1
output is forced high.
FIFO Control Register Description (Continued)
FCR Bit(s)
Description
FCR (7)
FCR (6)
Rx FIFO Trigger
Level (Bytes)
0
0
1
1
0
1
0
1
01
04
08
14
MCR
7
MCR
6
MCR
5
MCR
4
MCR
3
MCR
2
MCR
1
MCR
0
(RTS) Request to Send (Output High=0, Output Low=1)
(Out1) Output1 (Output1 Set High=0, Output1 Set Low=1)
(Out2) Output1 (Output2 Set High=0, Output2 Set Low=1)
(LOOP) Loopback Function (Disabled=0, Enabled=1)
Bit is set to “0”
Bit is set to “0”
Bit is set to “0”
(DTR) Data Terminal Ready (Output High=0, Output Low=1)
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