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參數資料
| 型號： | Z550 |
| 元件分類： | 通信、網絡模塊及開發工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數據通信 |
| 文件頁數： | 21/30頁 |
| 文件大?。?/td> | 581K |
| 代理商： | Z550 |
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I
Z550 UART
I
21
Oki Semiconductor
1. Typical condition is 3.3 V, T
j
= 25
°
C for typical process.
2. Limited by DLL/DLM reg.
3. f
X
= 8 MHz, divider value = 2.
4. Maximum 2
μ
s.
5. Maximum 1 RCLK cycle.
6. Maximum 1
μ
s.
Z550 UART Output Timing (10 MHz @ 3.3 V)
Parameter
Symbol
3 .3 V (Typ)
[1]
Units
DIS/DISN to drive disable delay
t
DD
t
DDD
t
HZ
t
HR
t
IRS
t
SI
t
STI
t
IR
t
SXA
t
WXI
t
MDO
t
SIM
t
RIM
N
1
ns
Delay from DIS/DISN to data
4
ns
DIS/DISN to floating data delay
2
ns
Delay from DOS/DOSN (WR THR) to reset interrupt
6
ns
Delay from initial INTR reset interrupt
< 16
BAUDOUT
Delay from initial write to interrupt
8 ~ 24
BAUDOUT
Delay from start bit low to interrupt (THRE) high
8
BAUDOUT
Delay from DIS/DISN (RD IIR) to reset interrupt (THRE)
4
ns
Delay from start to TXRDY active
< 8
BAUDOUT
Delay from write to TXRDY inactive
11
ns
Delay from DOS/DOSN (WR MCR) to output
4
ns
Delay to set interrupt from modem input
11
ns
Delay to reset interrupt for DIS/DISN (RS MSR)
4
ns
Baud divisor
[2]
ns
Baud output negative edge delay
t
BLD
t
BHD
t
LW
t
HW
t
SCD
t
SINT
t
RINT
3
ns
Baud output positive edge delay
3
ns
Baud output down time
125
ns
[3]
ns
[3]
Baud output up time
125
Delay from RCLK to sample time
[4]
μ
s
Delay from stop to set interrupt
[5]
RCLK
Delay from DIS/DISN (RD RBR/RDLSR) to reset interrupt
[6]
μ
s
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