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參數(shù)資料

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Z550 UART

Oki Semiconductor

4. IIR=02 (THRE interrupt) indicates that the Transmit Holding Register is empty. This interrupt is

cleared by ether writing a byte to the THR or by reading the IIR.

5. IIR=00 (Modem Status interrupt) indicates that there has been some change in the status of the

modem. This interrupt is cleared by reading the MSR, will also indicate what type of status change

occurred.

XMIT interrupts will occur as follows when the transmitter and XMIT FIFO interrupts are enabled

(FCR(0)=l, IER(l)=l)

1. The XMIT FIFO empty indications will be delayed one character time minus the last stop bit time

whenever THRE=1 and there have not been a minimum of two bytes at the same time in XMlT FIFO,

since the last THRE=1.

2. When the XMIT FIFO is empty, the transmitter holding register interrupt (IIR=02) occurs. The inter-

rupt is cleared as soon as the transmitter holding register is written to or the IIR is read.

When FCR(0) is enabled, an interrupt will not occur immediately even though it is enabled

(IER=1).The first XMIT interrupt occurs due to the conditions stated in 1 and 2 above only after data

has first been loaded into the XMIT FIFO.

XMIT FIFO empty interrupts have the same priority as RCVR FIFO trigger level and character trigger

change level interrupts.

FIFO Polled Mode Operation

Resetting IER(0), IER(l), IER(2), IER(3) all to zero, with FCR(0)=1, puts the ACE into the FIFO Polled Mode.

Since the RCVR and XMIT channels are controlled separately, ether or both can be operated in Polled

Mode.

In the FIFO Polled Mode, no timeout condition are indicated or trigger level reached. However, the RCVR

and XMIT FIFOs still have the capability of holding characters.

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