- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382738 > Z550 Telecomm/Datacomm PDF資料下載
參數(shù)資料
| 型號： | Z550 |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 7/30頁 |
| 文件大小： | 581K |
| 代理商： | Z550 |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
I
Z550 UART
I
7
Oki Semiconductor
Figure 3. Line Control Register
Line Control Register Description
LCR Bit(s)
Description
LCR(0) and
LCR(1)
Word length select bits. The number of bits in each serial character is programmed as shown below.
LCR(2)
Stop Bit Select. LCR(2) specifies the number of stop bits in each transmitted character. If LCR(2) is a logic “0”,
one stop bit is generated. If LCR(2) is a logic “1” when a 5 bit word length is selected, 1.5 stop bits are gener-
ated. If LCR(2) is a logic “1” when either a 6, 7, or 8 bit word length is selected, two stop bits are generated.
The receiver checks for two stop bits if programmed to do so.
LCR(3)
Parity Enable. When LCR(3) is high, a parity bit between the last data word bit and stop bit is generated and
checked.
LCR(4)
Even Parity Select. When parity is enabled [LCR(3) = 1], LCR(4) = 0 selects odd parity, and LCR(4) = 1 selects
even parity.
LCR(5)
Stick Parity. When parity is enabled [LCR(3) = 1], CLR(5) = 1 causes the transmission and reception of a parity
bit to be in the oppose state from that indicated by LCR(4). This allows parity to be forced to a known state
and the receiver to check the parity bit in a known state.
LCR(6)
Break Control. When LCR(6) is set to a logic “1”, the serial output (SOUT) is forced to the spacing (logic “0”)
state. The break is disabled by setting LCR(6) to a logic “0”. The Break Control bit acts only on SOUT and has
no effect on the transmitter logic. Break Control enables the CPU to alert a terminal in a computer communi-
cations system. If the following sequence is used, no invalid characters will be transmitted because of the
break.
Load all “0”s (pad character) in response to THRE.
Set the break in response to the next THRE.
Wait for the transmitter to be idle (TEMT = 1), then clear the break when normal transmission is restored.
LCR(7)
Divisor Latch Access Bit (DLAB). LCR(7) must be set high (logic “1”) to access the Divisor Latches DLL and
DLM of the Baud Rate Generator during read or write operations. LCR(7) must be set low (logic “0”) to access
the Receiver Buffer, the Transmitter Holding, or the interrupt Enable Registers.
LCR
7
LCR
6
LCR
5
LCR
4
LCR
3
LCR
2
LCR
1
LCR
0
Word Length Select
Stop Bit Select
Parity Enable
Even Parity Select
Stick Parity
Break Control
Divisor Latch Access Bit
LCR(1)
LCR(0)
Word Length
0
0
1
1
0
1
0
1
5 data bits
6 data bits
7 data bits
8 data bits
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Z5904 | Leaded Cartridge Fuse; Current Rating:1A; Voltage Rating:250V; Fuse Terminals:Axial Lead; Fuse Type:Time Delay; Body Material:Glass; Diameter:4.5mm; Fuse Size/Group:5 x 15 mm; Leaded Process Compatible:No; Length:14.48mm |
| Z6000(MLBA2) | FUSE,FAST ACTING,3A,250VAC |
| Z6005 | 3A 250V SLO-BLO NR 5X20MM |
| Z6006 | TANK SPRAY WASH |
| Z6011 | PCB PROCESSOR 3 SYSTEM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Z550LA40A | 制造商:HVCA & CKE 功能描述:RADIAL LEAD MOV - LINE VOLTAGE - STANDARD ENERGY, 1500V, 50A, 180PF |
| Z550LA80A | 制造商:HVCA & CKE 功能描述:Varistor, MO; 910V; 6500A; 350pF |
| Z550MC10 | 制造商:OMRON AUTOMATION AND SAFETY 功能描述:Z550 SENSOR HEAD 制造商:OMRON Industrial Automation 功能描述:Z550 SENSOR HEAD |
| Z550-MC10 | 制造商:OMRON AUTOMATION AND SAFETY 功能描述:Z550 SENSOR HEAD 制造商:OMRON Industrial Automation 功能描述:Z550 SENSOR HEAD 制造商:OMRON INDUSTRIAL AUTOMATION 功能描述:Z550 Sensor Head |
| Z550MC15 | 制造商:OMRON AUTOMATION AND SAFETY 功能描述:Z550 SENSOR HEAD |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。