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參數(shù)資料
| 型號： | Z550 |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 17/30頁 |
| 文件大小： | 581K |
| 代理商： | Z550 |
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I
Z550 UART
I
17
Oki Semiconductor
2. Clears the Line Status Register (LSR), except for Transmitter Shift Register Empty (TEMT) and Trans-
mit Holding Register Empty (THRE), which are set. When interrupts are subsequently enabled, an
interrupt occurs due to THRE. The Modem Control Register (MCR) is also cleared. All of the discrete
lines, memory elements and miscellaneous logic associated with these register bits are also cleared or
turned off. The Line Control Register (LCR), Divisor Latches, Receiver Buffer Register, and Transmit-
ter Buffer Register are not effected.
A summary of the effect of a reset on the ACE is given in the table below.
Following removal of the reset condition (MR low), the ACE remains in the idle mode until programmed.
Master Reset
If rclk is connected to the baudout signal, then while loading DLL and DLM registers, X’s appear on baud-
out pins and propagate through to the LSR register. Subsequent reads of this LSR register cause X’s to
appear on the data bus.
The following solutions can solve the above problem.
At the very beginning of simulation, until data is written into the DLL and DLM registers, hold rclk
to a known value (either “1” or “0”). The rclk input can be connected to baudout after writing data to
these registers. During real chip operation, the “1” or “0” value eventually propagates into the LSR
register, so this is not a design problem. Unknown states are created during simulation because
there is a feedback loop in the Z550 latch connection, and unknown states stay in latches
permanently once they have propagated there.
Instead of connecting baudout to rclk, leave these two signals altogether unconnected. Additional
external circuitry is then required to drive the receiver clock, rclk.
Reset the UART; write “1” to bit 7 of the LCR register; write any data into DDL and DLM; and
perform another reset. This procedure should not have any problems, although you will also have to
write new data into the DDL and DLM registers.
Register/Signal
Reset Control
Reset
Interrupt Enable Register
Reset
All bits low (0-3 forced and 4-7 permanent)
Interrupt Identification
Register
Reset
Bit 0 is high, Bits 1 and 2 low, Bits 3-7 are permanently low.
Line Control Register
Reset
All bits low.
MODEM Control Register
Reset
All bits low.
Line Status Register
Reset
All bits low, except bits 5 and 6.
MODEM Status Register
Reset
Bits 0-3 low, Bits 4-7 input signal.
SOUT
Reset
High
Interrupt (RCVR Errs)
Read LSR/Reset
Low
Interrupt (RCVR Data Ready)
Read RBR/Reset
Low
Interrupt (THRE)
Read IIR/Write THR/Reset
Low
Interrupt (Modem Status
Changes)
Read MSR/Reset
Low
Out 2
Reset
High
RTS
Reset
High
DTR
Reset
High
Out 1
Reset
High
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