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參數(shù)資料
| 型號： | Z550 |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 9/30頁 |
| 文件大?。?/td> | 581K |
| 代理商： | Z550 |
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I
Z550 UART
I
9
Oki Semiconductor
FIFO Control Register
The FIFO Control Register is a write only register at the same location as the IIR. It is used to enable and
clear the FIFOs, set the trigger level of the RCVR FIFO, and select the type of DMA signaling.
Figure 5. FIFO Control Register
LSR(5)
THRE indicates that the ACE is ready to accept a new character for transmission. The THRE bit is set high
when a character is transferred from the Transmitter Holding Roister into the Transmitter Shift Register.
LSR(5) is reset low by the loading of the Transmitter Holding Register by the CPU. LSR(5) is not reset by a
CPU read of the LSR. In FIFO Mode, when the XMlT FIFO is empty, this bit is set. It is cleared when one byte
is written to the XMlT Fife.
When the THRE interrupt is enabled IER(1), THRE causes a priority 3 interrupt in the IIR. If THRE is the in-
terrupt source indicated in IIR, lNTR is cleared by a read of the IIR.
LSR(6)
Transmitter Empty (TEMT). TEMT is set high when the Transmitter Holding Register (THR) and the Trans-
mitter Shift Register (TSR) are both empty. LSR(6) is reset low when a character is loaded into the THR and
remains low until the character is transferred out of SOUT. TEMT is not reset low by a CPU read of the LSR.
In the FIFO Mode, when both the transmitter FIFO and shift register are empty, this bit is set to one.
LSR(7)
This bit is always 0 in the Z450 Mode. In FIFO Mode, it is set when at least one of the following data errors
is in the FIFO: Parity Error, Framing Error or Break Interrupt indication.
FIFO Control Register Description
FCR Bit(s)
Description
FCR(0)
FIFO ENABLE. Enables both the XMlT and RCVR FIFOs. Programming of other FCR bits is enabled by set-
ting FCR(0)=1. The FIFOs operate in Z450 mode when FCR(0)=0. All bytes in both FIFOs can be cleared au-
tomatically from the FIFOs when changing from FIFO mode to Z450 mode and vice versa.
FCR(1)
RCVR FIFO Reset. This bit clears all bytes in the RCVR FIFO and resets the counter logic to 0 when it is set
to a one. It does not clear the receive shift register.
FCR(2)
XMlT FIFO Reset. This bit clears all bytes in the XMlT FIFO and resets the counter logic to 0 when it is set
to a one. This does not clear the transmit shift register.
Line Status Register Description (Continued)
LSR Bit(s)
Description
FCR
7
FCR
6
FCR
5
FCR
4
FCR
3
FCR
2
FCR
1
FCR
0
Receiver FIFO Reset (Reset Rx FIFO = 1)
Transmit FIFO Reset (Reset Tx FIFO = 1)
DMA Mode Select (DMA Mode 1 = 1, DMA Mode 0 = 0)
Not Used
Receiver FIFO Interrupt Trigger Level
FIFO Enable (FIFO Enable = 1)
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