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參數(shù)資料
| 型號(hào)： | Z550 |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開(kāi)發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁(yè)數(shù)： | 4/30頁(yè) |
| 文件大?。?/td> | 581K |
| 代理商： | Z550 |
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Z550 UART
I
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4
Oki Semiconductor
SIGNAL DESCRIPTIONS
Signal Name
Type
Fan-In
Fan-Out
Max
Signal Description
DI 0-7
I
1
-
Data Input. Data Inputs 0-7 are used to transfer data and control information
from the external system to the ACE. DI0 is the first data bit to be transferred.
CS 0-1, 2N
I
1
-
Chip Select. The device is selected when CS0 and CS1 are high and CS2N is
low.
A 0-2
I
1
-
Address. Address Lines 0-2 select the internal registers.
ADSN
I
1.6
-
Address Strobe. The state of the Chip Select and Address Lines are latched
when ADSN is low.
DIS
I
1
-
Read Strobe. Data transfers from the ACE to the output data bus when DIS is
high.
DISN
I
1
-
Read Strobe. Same as DIS but active low.
DOS
I
1
-
Write Strobe. Data transfers from the input data bus to the ACE when DIS is
high.
DOSN
I
1
-
Write Strobe. Same as DOS but active low.
CLK
I
1
-
Clock. Input for external timing reference.
MR
I
1
-
Master Reset. A high level resets the device, forcing the ACE into an idle state
and suspends all data activity until programmed to resume. The MCR and its
output is cleared. The LSR is cleared except for the THRE and TEMT bits,
which are both sets.
CTS
I
1
-
Clear To Send. The state of CTS can be read from bit 4 (CTS) of the MSR. Bit
0 (DCTS) of the MSR is set if the CTS input changes state since the last time
the MSR was read. CTS low indicates to the ACE that data on SOUT can be
transmitted.
DSR
I
1
-
Data Send Ready. The state of DSR can be read from bit 5 (DSR) of the MSR.
Bit 1 (DDSR) of the MSR is set if the DSR input changes state since the last
time the MSR was read. DSR low indicates to the ACE that there is data ready
for it to receive.
RI
I
1
-
Ring Indicator. A low signal indicates that a telephone ringing signal has
been received by the modem. The state of RI can be read from bit 6 (RI) of the
MSR. Bit 2 (TERI) of the MSR is set if the RI input changes from high to low
since the last time the MSR was read.
DCD
I
1
-
Data Carrier Detect. The DCD signal indicates that the data carrier has been
detected by the modem. The state of DCD can be read from bit 7 (DCD) of the
MSR. Bit 3 (DDCD) of the MSR is set if the DCD input changed state since the
last time the MSR is read.
RCLK
I
5
-
Receive Clock. This signal is an external input to the ACE's receiver logic (it
is 16X the SIN data rate).
SIN
I
2.5
-
Serial Input. The Serial Input receives serial data from the modem or other se-
rial data source into the ACE.
DO 0-4
DO5
DO6-7
O
-
16
19
16
Data Output. Data Outputs 0-7 are used to transfer data and status informa-
tion from the ACE to your system. DI0 is the first data bit to be received.
OE
O
-
40
Output Enable. This signal is a 3-state control used to configure the LSI pins
of the ASIC for production testing.
DDIS
O
-
15
Driver Disable. The macrocell asserts this signal LOW while the system is
reading data from the ACE.
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