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參數(shù)資料
| 型號： | Z550 |
| 元件分類： | 通信、網(wǎng)絡模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 18/30頁 |
| 文件大小： | 581K |
| 代理商： | Z550 |
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I
Z550 UART
I
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18
Oki Semiconductor
Programming
The serial channel of the ACE is programmed by the control registers; LCR, IER, DLL and DLM, and MCR.
These control words define the character length, number of stop bits, parity, baud rate, and modem inter-
face.
While the control registers can be written to in any order, the IER should be written to last because it con-
trols the interrupt enables. Once the serial channel is programmed and operational, these registers can be
updated any time the serial channel is not transmitting or receiving data.
FIFO Interrupt Mode Operation
The following RCVR interrupts will occur when the RCVR FIFO and receive interrupts are enabled.
interrupts reflect the byte at the top of the FIFO
.
priority.
All
The interrupt descriptions are in order of decreasing
1. IIR=01 indicates that there are no interrupts pending.
2. IIR=06 (Receive Line Status Interrupt) indicates that the byte at the top of the FIFO has some sort of
error in it (OE, PE, FE, or BI). This interrupt is cleared by reading the LSR. Reading the LSR will also
indicate which one of the errors is in that byte.
3. The IIR will equal an 04 when received data is available in the RCVR FIFO. In Mode 0, this occurs
when a complete character is transferred from the receiver shift register to the RCVR FIFO. In Mode
1, the RCVR FIFO must be filled at or above the trigger level with data. This interrupt is cleared by
reading the data f from the RBR, until it either is empty (Mode 0) or the amount of data in it is less
than the trigger level (Mode 1). LSR(0)=1 indicates that the data in the top byte in the RCVR FIFO is
available, When the FIFO is emptied by reading the Receive Buffer Register, LSR(0) is reset to a zero.
The Trigger Level Change interrupt (IIR = 0C) description is found in the following section. It has the
same priority as the Receiver Data Available interrupt (IIR = 04).
A. If the following conditions exist, a FIFO trigger change level interrupt will occur.
Minimum of one character in FIFO.
Last received serial character was longer than 3.5 to 4.5 continuous previous character times (if
two stop lets are programmed, the second one is included in the time delay) Once 3.5 character
times have been met and no accesses have been made to the FIFO, the trigger level matches the
number of FIFO characters and the trigger change level interrupt will be returned to its original
programmed value.
The last CPU read of the FIFO was more than 3.5 to 4.5 continuous character times ago. At 300
baud with 12 bit characters, the FIFO timeout interrupt causes a latency of 160ms maximum,
from received character to interrupt issued.
B. By using the RCLK input for a clock signal, the character times can be calculated. (The delay is
proportional to the baud rate.)
C. The trigger change level timer is reset after the CPU reads the RCVR FIFO or after a new character
is received when there has been no trigger change level interrupt.
D. A trigger change level interrupt is cleared and the timer is reset when the CPU reads a character
from the RCVR FIFO.
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