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Z550 UART
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11
Oki Semiconductor
Modem Status Register
The Modem Status Register (MSR) provides the CPU with status of the modem input lines from modems
or peripheral devices. The MSR allows the CPU to read the serial channel modem signal inputs by access-
ing the data bus interface of the ACE. In addition to the current status information, four bits of the MSR
indicate whether the modem inputs have changed since the last reading of the MSR. The delta status bus
are set high when a control input from the modem changes state, and reset low when the CPU reads the
MSR.
The modem input lines are CTS, DSR, RI, and DCD. MSR(4) - MSR(7) are status indications of these lines.
A status bit = 1 indicates the input is a low. A status bit = 0 indicates the input is high. If the modem status
interrupt in the Interrupt Enable Register is enabled [IER(3)=1] an interrupt is generated whenever
MCR(3):
When MCR(3) is set high, the OUT2 output is forced low. When MCR(3) is reset low, the OUT2
output is forced high.
MCR(4):
MCR(4) provides a local loop back feature for diagnostic testing. When MCR(4) is set high, Serial
Output (SOUT) is set to the marking (logic “1”) state. The receiver data input, Serial Input (SIN)
is disconnected and the output of the Transmitter Shift Register is looped back into the Receiver
Shift Register input. The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected.
The four MCR bits DTR, RTS, OUT1, and OUT2 are internally connected to MSR(5), MSR(4),
MSR(6), and MSR(7) in that order. The modem control output pins are forced to their inactive
state (high).
In the diagnostic mode, data transmitted is immediately received. This allows the processor to
verify the transmit and receive data paths of the selected serial channel.
Interrupt control is fully operational. However, interrupts are generated by controlling the lower
four MCR bits internally. Interrupts are not generated by activity on the external pins represented
by those four bus.
Bits MCR(5) - MCR(7):
Permanently set to logic “0”.
Modem Control Register Description (Continued)
MCR Bit(s)
Bit Description