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參數資料
| 型號： | Z550 |
| 元件分類： | 通信、網絡模塊及開發工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數據通信 |
| 文件頁數： | 20/30頁 |
| 文件大小： | 581K |
| 代理商： | Z550 |
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I
Z550 UART
I
––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
20
Oki Semiconductor
AC CHARACTERISTICS
1. Typical condition is 3.3 V, T
j
2. Applicable only when ADSN is tied low.
= 25
°
C for typical process.
Z550 UART Input Timing (10 MHz @ 3.3V)
Parameter
Symbol
3.3 V (Typ)
[1]
Units
Address strobe width
t
ADS
t
AS
t
AH
t
CS
t
CH
t
DIW
t
RC
RC
5
ns
Address setup time
11
ns
Address hold time
0
ns
Chip select setup time
12
ns
Chip select hold time
0
ns
DIS/DISN Strobe Width
15
ns
Read Cycle Delay
Read Cycle = t
AR [2]
+ t
DIW
+ t
RC
DOS/DOSN strobe width
0
ns
24
ns
t
DOW
t
WC
WC
11
ns
Write cycle delay
4
ns
Write cycle = t
AW
+ t
DOW
+ t
WC
Data setup time
25
ns
t
DS
t
DH
t
RA
t
RCS
t
AR
t
CSR
t
WA
t
WCS
t
AW
t
CSW
t
MRW
t
XH
t
XL
8
ns
Data hold time
Address hold time from DIS/DISN
[2]
Chip select hold time from DIS/DISN
[2]
DIS/DISN delay from address
[2]
DIS/DISN delay from chip select
[2]
Address hold time from DOS/DOSN
[2]
Chip select hold time from DOS/DOSN
[2]
DOS/DOSN delay from address
[2]
DOS/DOSN delay from select
[2]
5
ns
0
ns
0
ns
9
ns
0
ns
0
ns
0
ns
10
ns
0
ns
Master reset pulse width
15
ns
Duration of clock high pulse
15
ns
Duration of clock low pulse
7
ns
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