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參數資料
| 型號： | Z550 |
| 元件分類： | 通信、網絡模塊及開發工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數據通信 |
| 文件頁數： | 13/30頁 |
| 文件大小： | 581K |
| 代理商： | Z550 |
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I
Z550 UART
I
13
Oki Semiconductor
Interrupt Identification Register
The Interrupt Identification Register (IIR) in the serial channel of the ACE provides interrupt interfacing
capability. To minimize software overhead, the serial channel prioritizes interrupts into four levels. The
four levels of interrupt conditions are:
Interrupt Priorities
Information indicating that a prioritized interrupt is pending and the type of interrupt is stored in the
Interrupt Identification Register (IIR). When addressed during chip select time, the IIR indicates the high-
est priority interrupt pending. No other interrupts are acknowledged until that interrupt is serviced by
the CPU. The contents of the IIR is shown in the following tables.
Interrupt Identification Register Bits
Interrupt Condition
Priority
Receiver Line Status
1
Received Data Ready
2
Transmitter Holding Register Empty
3
Modem Status
4
IIR Bit(s)
Bit Description
IIR(0)
When IIR(0) is low, an interrupt is pending. When IIR(0) is high, no interrupt is pending.
IIR(1) and IIR(2)
These two bits are used to identify the highest priority interrupt pending as indicated in the following
table.
IIR(3)
This bit is always logic “0” in Z450 Mode. In FIFO Mode, this bit is set along with IIR(2) when a timeout
interrupt is pending.
IIR(4) and IIR(5)
These bits of the IIR are always logic “0”.
IIR(6) and IIR(7)
FRC(0)=1 sets these bits to logic “1”.
Interrupt Identification (IIR) Register Description
FIFO
Mode
Only
Interrupt Identification
Interrupt Set and Reset Functions
Bit 3
Bit 2
Bit 1
Bit 0
Priority
Level
Interrupt Flag
Interrupt Source
Interrupt Reset Control
0
0
0
1
-
None
None
–
0
1
1
0
First
Receiver Line
Status
OE, PE, FE, or BI
LSR Read
0
1
0
0
Second
Received Data
Available
Receiver data available for 450
or 550 mode, or trigger level
reached for FIFO mode
RBR read or FIFO drops
below the trigger level
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