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參數資料
| 型號： | Z550 |
| 元件分類： | 通信、網絡模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數據通信 |
| 文件頁數： | 5/30頁 |
| 文件大小： | 581K |
| 代理商： | Z550 |
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I
Z550 UART
I
5
Oki Semiconductor
DTR
O
-
16
Data Terminal Ready. The macrocell sets this signal LOW when a logic 1 has
bene written to bit 0 (DTR) of the MCR. This signal is set high when a logic 0
is written to bit 0 of the MCR or whenever a reset occurs. A low DTR indicates
that the ACE is ready to receive data.
RTS
O
-
16
Request To Send. This signal is set low by writing a logic 1 to bit 1 of the MCR.
It is set high when a logic 0 is written to bit 1 of the MCR or whenever a reset
occurs. A low RTS signal indicates that the ACE has data ready to transmit.
OUT1
O
-
16
Output 1. This output is set low by writing a logic 1 to bit 2 of the MCR, and
set high by writing a logic 0 to bit 2 of the MCR.
OUT2
O
-
16
Output 2. This output is set low by writing a logic 1 to bit 3 of the MCR, and
set high by writing a logic 0 to bit 3 of the MCR.
SOUT
O
-
19
Serial Data Out. This output is the serial data output of the ACE's transmitter
circuitry.
INTR
O
-
18
Interrupt. The Interrupt output goes high whenever a Transmitter Holding
Register Empty, Received Data Available, Receiver Error Flag, Modem Status
condition or Trigger Charge Timeout (in FIFO mode) is detected and it is en-
abled in the IER.
BAUD
O
-
15
Baud Rate Out. This signal is the output of the internal Baud Rate Generator.
TXRDY
O
-
19
Transmit Ready. this signal provides two types of DMA signaling selected by
bit 3 of the FCR when operating with the FIFO's enabled.
In mode 0 (bit 3 of the FCR = 0), TXRDY will be active (= 0) when the XMIT FIFO
and XMIT holding register contain no characters. TXRDY will go high when
the first character is loaded into the holding register of the XMIT FIFO. This
mode is normally used for single transfer DMA operation.
In mode 1 (bit 3 of the FCR = 1), TXRDY will be active (=0) when there are no
characters in the XMIT FIFO. TXRDY will go high when the XMIT FIFO is com-
pletely full. This mode is normally used when continual multiple transfers,
that fill the FIFO, are made.
NOTE: If the FIFO's are disabled (FIFO mode 0) only single DMA transfers are
allowed.
RXRDY
O
-
19
Receiver Ready. this signal provides two types of DMA signaling selected by
bit 3 of the FCR when operating with the FIFO's enabled.
In mode 0 (bit 3 of the FCR = 0), RXRDY will be active (=0) when the RCVR
FIFO and RCVR holding register contain at least one characters. RXRDY will
go high when there are no more characters in the FIFO or holding register.
This mode is normally used for single transfer DMA operation.
In mode 1 (bit 3 of the FCR = 1), RXRDY will be active (=0) when the timeout
or trigger levels are reached. RXRDY will go high when the FIFO or holding
register is empty. This mode is normally used when continual multiple trans-
fers, that fill the FIFO, are made.
NOTE: If the FIFO's are disabled (FIFO mode 0) only single DMA transfers are
allowed.
SIGNAL DESCRIPTIONS
(CONTINUED)
Signal Name
Type
Fan-In
Fan-Out
Max
Signal Description
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