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參數資料
| 型號： | Z550 |
| 元件分類： | 通信、網絡模塊及開發工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數據通信 |
| 文件頁數： | 6/30頁 |
| 文件大小： | 581K |
| 代理商： | Z550 |
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Z550 UART
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6
Oki Semiconductor
FUNCTIONAL DESCRIPTION
Registers
Three types of internal registers are used in the ACE. The three types are the Control, Status, and Data
registers. The control registers are the Bit Rate Select Register DLL (Divisor Latch LSB) and DLM (Divisor
Latch MSB), Line Control Register, Interrupt Enable Register, and the Modem Control Registers. The sta-
tus registers are the Line Status Registers and the Modem Status Register. The data registers are the
Receiver Buffer Register and the Transmitter Holding Register. The Address, Read, and Write inputs are
used in conjunction with the Divisor Latch Access Bit in the Line Control Register [LCR(7)] to select the
register to be written or read (see the table below). Individual bits within these registers are referred to by
the register mnemonic and the bit number in parenthesis. As an example, LCR(7) refers to Line Control
Register Bit 7.
Serial Channel Internal Register
[1]
[2]
Transmitter Buffer Register and Receiver Buffer Register
The Transmitter Buffer Register and Receiver Buffer Register are data registers that hold from five to eight
bits of data. If less than eight data bits are transmitted, data is right justified to the LSB. Bit 0 of a data word
is always the first serial data bit received and transmitted. The ACE data registers are double-buffered so
that read and write operations may be performed when the UART is performing the parallel-to-serial or
serial-to-parallel conversion.
Line Control Register
The format of the data character is controlled by the Line Control Register. The contents of the LCR may
be read, eliminating the need for separate storage of the line characteristics in system memory. The con-
tents of the LCR is shown in
Figure 3
and described in the following table.
1. X = “Don’t Care”, 0 = Logic Low, 1 = Logic High.
2. The serial channel is accessed when –CS0 is low.
DLAB
A2
A1
A0
Mnemonic
Register
0
0
0
X
X
X
X
X
X
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
RBR
THR
IER
IIR
LCR
MCR
LSR
MSR
SCR
DDL
DLM
Receiver Buffer Register (read only)
Transmitter Holding Register (write only)
Interrupt Enable Register
Interrupt Identification Register (read only)
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratch Register
Divisor Latch (LSB)
Divisor Latch (MSB)
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