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參數資料
型號: ADUC845
廠商: Analog Devices, Inc.
元件分類: ADC
英文描述: MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU
中文描述: MicroConverter的多通道ADC的24-/16-Bit與嵌入式62 kB閃存以及單周期控制器
文件頁數: 11/108頁
文件大小: 1109K
代理商: ADUC845
ADuC845/ADuC847/ADuC848
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. A | Page 11 of 108
52 51 50 49 48
43 42 41 40
47 46 45 44
14 15 16 17 18 19 20 21 22 23 24 25 26
1
2
3
4
5
6
7
8
9
10
11
13
12
PIN 1
(TOP VIEW
39
38
37
36
35
34
33
32
31
30
29
28
27
P
P
P
P
D
D
D
P
P
P
P
A
P
E
D
R
P
P
P
P
D
D
P
P
P
P
S
2
C
P1.0/AIN1
P1.1/AIN2
P1.2/AIN3/REFIN2+
P1.3/AIN4/REFIN2–
AV
DD
AGND
REFIN–
REFIN+
P1.4/AIN5
P1.5/AIN6
P1.6/AIN7/IEXC1
P1.7/AIN8/IEXC2
AINCOM/DAC
P2.7/PWMCLK
P2.6/PWM1
P2.5/PWM0
P2.4/T2EX
DGND
DV
DD
XTAL2
XTAL1
P2.3/SS/T2
P2.2/MISO
P2.1/MOSI
P2.0/SCLOCK (SPI)
SDATA
D
0
ADuC845/ADuC847/ADuC848
Figure 2. 52-Lead MQFP Pin Configuration
P1.1/AIN2
P1.2/AIN3/REFIN2+
P1.3/AIN4/REFIN2–
AGND
AGND
REFIN–
REFIN+
P1.4/AIN5
AV
DD
P1.5/AIN6
P1.6/AIN7/IEXC1
P1.7/AIN8/IEXC2
AINCOM/DAC
DAC
A
A
R
P
P
P
P
D
D
D
P
P
P
P
S
2
C
P2.7/PWMCLK
P2.6/PWM1
P2.5/PWM0
P2.4/T2EX
DGND
DGND
DV
DD
XTAL2
XTAL1
P2.3/SS/T2
P2.2/MISO
P2.1/MOSI
P2.0/SCLOCK (SPI)
SDATA
P
P
P
P
P
D
D
D
P
P
P
P
A
P
E
14
1
2
3
4
5
6
7
8
9
10
11
12
13
1
1
1
1
1
2
2
2
2
2
2
2
2
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
4
4
4
4
4
4
5
5
5
5
5
5
5
PIN 1
4
(TOP VIEW
0
ADuC845/ADuC847/ADuC848
Figure 3. 56-Lead CSP Pin Configuration
Table 3. Pin Function Descriptions
Pin No:
52-MQFP
56-CSP
1
56
Pin No:
Mnemonic
P1.0/AIN1
Type
1
I
Description
By power-on default, P1.0/AIN1 is configured as the AIN1 analog input.
AIN1 can be used as a pseudo differential input when used with AINCOM or as
the positive input of a fully differential pair when used with AIN2.
P1.0 has no digital output driver. It can function as a digital input for which 0
must be written to the port bit. As a digital input, this pin must be driven high or
low externally.
On power-on default, P1.1/AIN2 is configured as the AIN2 analog input.
AIN2 can be used as a pseudo differential input when used with AINCOM or as
the negative input of a fully differential pair when used with AIN1.
P1.1 has no digital output driver. It can function as a digital input for which 0
must be written to the port bit. As a digital input, this pin must be driven high or
low externally.
On power-on default, P1.2/AIN3 is configured as the AIN3 analog input.
AIN3 can be used as a pseudo differential input when used with AINCOM or as
the positive input of a fully differential pair when used with AIN4.
P1.2 has no digital output driver. It can function as a digital input for which 0
must be written to the port bit. As a digital input, this pin must be driven high or
low externally. This pin also functions as a second external differential reference
input, positive terminal.
On power-on default, P1.3/AIN4 is configured as the AIN4 analog input.
AIN4 can be used as a pseudo differential input when used with AINCOM or as
the negative input of a fully differential pair when used with AIN3.
P1.3 has no digital output driver. It can function as a digital input for which 0
must be written to the port bit. As a digital input, this pin must be driven high or
low externally. This pin also functions as a second external differential reference
input, negative terminal.
Analog Supply Voltage.
Analog Ground.
A second analog ground is provided with the CSP version only.
2
1
P1.1/AIN2
I
3
2
P1.2/AIN3/REFIN2+
I
4
3
P1.3/AIN4/REFIN2
I
5
6
---
Footnotes at end of table.
4
5
6
AV
DD
AGND
AGND
S
S
S
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