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參數資料
| 型號： | ADUC845 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| 中文描述： | MicroConverter的多通道ADC的24-/16-Bit與嵌入式62 kB閃存以及單周期控制器 |
| 文件頁數： | 62/108頁 |
| 文件大小： | 1109K |
| 代理商： | ADUC845 |
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C peripheral addresses for the part. It may be overwritten by user code. Application Note
uC001 at
describes the format of the I2
C standard 7-bit address.
9BH
55H
No
SFR Address:
Power-On Default:
Bit Addressable:
I2CADD1—I
2
C Address Register 2
Function:
SFR Address:
Power-On Default:
Bit Addressable:
Same as the I2CADD.
F2H
7FH
No
I2CDAT—I
2
C Data Register
Function:
The I2CDAT SFR is written to by user code to transmit data, or read by user code to read data just received by
the I
2
C interface. Accessing I2CDAT automatically clears any pending I
2
C interrupt and the I2CI bit in the
I2CCON SFR. User code should access I2CDAT only once per interrupt cycle.
9AH
00H
No
SFR Address:
Power-On Default:
Bit Addressable:
The main features of the MicroConverter I
2
C interface are
Only two bus lines are required: a serial data line (SDATA)
and a serial clock line (SCLOCK).
An I
2
C master can communicate with multiple slave
devices. Because each slave device has a unique 7-bit
address, single master/slave relationships can exist at all
times even in a multislave environment.
The ability to respond to two separate addresses when
operating in slave mode.
On-chip filtering rejects <50 ns spikes on the SDATA and
the SCLOCK lines to preserve data integrity.
DV
DD
I
2
C
MASTER
I
2
C
SLAVE 1
I
2
C
SLAVE 2
0
Figure 45. Typical I
2
C System
Software Master Mode
The ADuC845/ADuC847/ADuC848 can be used as an I
2
C
master device by configuring the I
2
C peripheral in master mode
and writing software to output the data bit-by-bit. This is
referred to as a software master. Master mode is enabled by
setting the I2CM bit in the I2CCON register.
To transmit data on the SDATA line, MDE must be set to enable
the output driver on the SDATA pin. If MDE is set, the SDATA
pin is pulled high or low depending on whether the MDO bit is
set or cleared. MCO controls the SCLOCK pin and is always
configured as an output in master mode. In master mode, the
SCLOCK pin is pulled high or low depending on the whether
MCO is set or cleared.
To receive data, MDE must be cleared to disable the output
driver on SDATA. Software must provide the clocks by toggling
the MCO bit and reading the SDATA pin via the MDI bit. If
MDE is cleared, MDI can be used to read the SDATA pin. The
value of the SDATA pin is latched into MDI on a rising edge of
SCLOCK. MDI is set if the SDATA pin is high on the last rising
edge of SCLOCK. MDI is cleared if the SDATA pin is low on
the last rising edge of SCLOCK.
Software must control MDO, MCO, and MDE appropriately to
generate the start condition, slave address, acknowledge bits,
data bytes, and stop conditions. These functions are described
in Application Note uC001.
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| ADUC845BCP62-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
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