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參數(shù)資料
型號: ADUC845
廠商: Analog Devices, Inc.
元件分類: ADC
英文描述: MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU
中文描述: MicroConverter的多通道ADC的24-/16-Bit與嵌入式62 kB閃存以及單周期控制器
文件頁數(shù): 86/108頁
文件大小: 1109K
代理商: ADUC845
ADuC845/ADuC847/ADuC848
IEIP2—Secondary Interrupt Enable Register
Rev. A | Page 86 of 108
SFR Address:
Power-On Default:
Bit Addressable:
A9H
A0H
No
Table 60. IEIP2 Bit Designations
Bit No.
Name
7
----
6
PTI
5
PPSM
4
PSI
3
----
2
ETI
Description
Not Implemented. Write Don’t Care.
Time Interval Counter Interrupt Priority Setting (1 = High, 0 = Low).
Power Supply Monitor Interrupt Priority Setting (1 = High, 0 = Low).
SPI/I
2
C Interrupt Priority Setting (1 = High, 0 = Low).
This bit must contain 0.
Set by the user to enable the time interval counter interrupt.
Cleared by the user to disable the time interval counter interrupt.
Set by the user to enable the power supply monitor interrupt.
Cleared by the user to disable the power supply monitor interrupt.
Set by the user to enable the SPI/I
2
C serial port interrupt.
Cleared by the user to disable the SPI/I
2
C serial port interrupt.
1
EPSMI
0
ESI
INTERRUPT PRIORITY
The interrupt enable registers are written by the user to enable
individual interrupt sources; the interrupt priority registers
allow the user to select one of two priority levels for each
interrupt. A high priority interrupt can interrupt the service
routine of a low priority interrupt, and if two interrupts of
different priorities occur at the same time, the higher level
interrupt is serviced first. An interrupt cannot be interrupted by
another interrupt of the same priority level. If two interrupts of
the same priority level occur simultaneously, the polling sequence,
as shown in Table 61, is observed.
Table 61. Priority within Interrupt Level
Source
Priority
Description
PSMI
1 (Highest)
Power Supply Monitor Interrupt
WDS
2
Watchdog Timer Interrupt
IE0
2
External Interrupt 0
RDY0/RDY1
3
ADC Interrupt
TF0
4
Timer/Counter 0 Interrupt
IE1
5
External Interrupt 1
TF1
6
Timer/Counter 1 Interrupt
ISPI/I2CI
7
SPI/I
2
C Interrupt
RI/TI
8
UART Serial Port Interrupt
TF2/EXF2
9
Timer/Counter 2 Interrupt
TII
11 (Lowest)
Timer Interval Counter Interrupt
INTERRUPT VECTORS
When an interrupt occurs, the program counter is pushed onto
the stack, and the corresponding interrupt vector address is
loaded into the program counter. The interrupt vector addresses
are shown in Table 62.
Table 62. Interrupt Vector Addresses
Source
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
RDY0/RDY1 (ADuC845 only)
ISPI/I2CI
PSMI
TII
WDS
Vector Address
0003H
000BH
0013H
001BH
0023H
002BH
0033H
003BH
0043H
0053H
005BH
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