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參數資料
| 型號： | ADUC845 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| 中文描述： | MicroConverter的多通道ADC的24-/16-Bit與嵌入式62 kB閃存以及單周期控制器 |
| 文件頁數： | 69/108頁 |
| 文件大小： | 1109K |
| 代理商： | ADUC845 |
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ADuC845/ADuC847/ADuC848
WATCHDOG TIMER
The watchdog timer generates a device reset or interrupt within a
reasonable amount of time if the ADuC845/ADuC847/
ADuC848 enters an erroneous state, possibly due to a program-
ming error or electrical noise. The watchdog function can be
disabled by clearing the WDE (watchdog enable) bit in the
watchdog control (WDCON) SFR. When enabled, the watchdog
circuit generates a system reset or interrupt (WDS) if the user
program fails to set the WDE bit within a predetermined amount
of time (see the PRE3…0 bits in Table 44). The watchdog timer
Table 44. WDCON SFR Bit Designations
Bit No.
Name
7, 6, 5, 4
PRE3, PRE2, PRE1, PRE0
Rev. A | Page 69 of 108
is clocked from the 32 kHz external crystal connected between
the XTAL1 and XTAL2 pins. The WDCOM SFR can be written
only by user software if the double write sequence described in
WDWR is initiated on every write access to the WDCON SFR.
WDCON—Watchdog Control Register
SFR Address:
Power-On Default:
Bit Addressable:
C0H
10H
Yes
Description
Watchdog Timer Prescale Bits.
The watchdog timeout period is given by the equation
t
WD
= (2
PRE
× (2
9
/ f
XTAL
)) (0 ≤ PRE ≤ 7; f
XTAL
= 32.768 kHz)
PRE3
PRE2
PRE1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
PRE3–0 > 1000b
Watchdog Interrupt Response Enable Bit.
If this bit is set by the user, the watchdog generates an interrupt response instead of a system reset
when the watchdog timeout period expires. This interrupt is not disabled by the CLR EA instruction,
and it is also a fixed, high priority interrupt. If the watchdog timer is not being used to monitor the
system, it can be used alternatively as a timer. The prescaler is used to set the timeout period in
which an interrupt is generated.
Watchdog Status Bit.
Set by the watchdog controller to indicate that a watchdog timeout has occurred.
Cleared by writing a 0 or by an external hardware reset. It is not cleared by a watchdog reset.
Watchdog Enable Bit.
Set by the user to enable the watchdog and clear its counters. If this bit is not set by the user within
the watchdog timeout period, the watchdog timer generates a reset or interrupt, depending on
WDIR.
Cleared under the following conditions: user writes 0; watchdog reset (WDIR = 0); hardware reset;
PSM interrupt.
Watchdog Write Enable Bit.
Writing data to the WDCON SFR involves a double instruction sequence. Global interrupts must first
be disabled. The WDWR bit is set with the very next instruction, a write to the WDCON SFR. For
example:
CLR EA ;Disable Interrupts while configuring to WDT
SETB WDWR ;Allow Write to WDCON
MOV WDCON, #72H ;Enable WDT for 2.0s timeout
SETB EA ;Enable Interrupts again (if required)
PRE0
0
1
0
1
0
1
0
1
0
Timeout Period (ms)
15.6
31.2
62.5
125
250
500
1000
2000
0.0
Action
Reset or interrupt
Reset or interrupt
Reset or interrupt
Reset or interrupt
Reset or interrupt
Reset or interrupt
Reset or interrupt
Reset or interrupt
Immediate reset
Reserved. Not a valid selection.
3
WDIR
2
WDS
1
WDE
0
WDWR
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