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參數資料
| 型號： | ADUC845 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| 中文描述： | MicroConverter的多通道ADC的24-/16-Bit與嵌入式62 kB閃存以及單周期控制器 |
| 文件頁數： | 46/108頁 |
| 文件大小： | 1109K |
| 代理商： | ADUC845 |
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ADuC845/ADuC847/ADuC848
SF (ADC SINC FILTER CONTROL REGISTER)
The SF register is used to configure the decimation factor for the ADC, and therefore, has a direct influence on the ADC throughput rate.
Rev. A | Page 46 of 108
SFR Address:
Power-On Default:
Bit Addressable:
D4H
45H
No
Table 28. Sinc Filter SFR Bit Designations
SF.7
SF.6
0
1
SF.5
0
SF.4
0
SF.3
0
SF.2
1
SF.1
0
SF.0
1
The bits in this register set the decimation factor of the ADC. This has a direct bearing on the throughput rate of the ADC along with the
chop setting. The equations used to determine the ADC throughput rate are
Fadc (Chop On)
=
SFword
×
×
8
3
1
× 32.768 kHz
where
SFword
is in decimal.
Fadc (Chop Off)
=
SFword
×
8
1
× 32.768 kHz
where
SFword
is in decimal.
Table 29. SF SFR Bit Examples
Chop Enabled (ADCMODE.3 = 0)
SF (Decimal)
SF (Hexadecimal)
13
1
0D
69
45
82
52
255
FF
Chop Disabled (ADCMODE.3 = 1)
SF (Decimal)
SF (Hexadecimal)
3
03
69
45
82
52
255
FF
Fadc (Hz)
105.3
19.79
16.65
5.35
Tadc (ms)
9.52
50.53
60.06
186.77
Tsettle (ms)
19.04
101.1
120.1
373.54
Fadc (Hz)
1365.3
59.36
49.95
16.06
Tadc (ms)
0.73
16.84
20.02
62.25
Tsettle (ms)
2.2
50.52
60.06
186.8
1
With chop enabled, if an SF word smaller than 13 is written to this SF register, the filter automatically defaults to 13.
During ADC calibration, the user-programmed value of SF word is used. The SF word does not default to the maximum setting (255) as it
did on previous MicroConverter products. However, for optimum calibration results, it is recommended that the maximum SF word be set.
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| ADUC845BCP62-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
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