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參數資料
| 型號： | ADUC845 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| 中文描述： | MicroConverter的多通道ADC的24-/16-Bit與嵌入式62 kB閃存以及單周期控制器 |
| 文件頁數： | 57/108頁 |
| 文件大小： | 1109K |
| 代理商： | ADUC845 |
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ADuC845/ADuC847/ADuC848
PWM Cycle Width High Byte (PWM1H)
SFR Address:
Power-On Default:
Bit Addressable:
Rev. A | Page 57 of 108
B4H
00H
No
Table 37. PWM1H: PWM Cycle Width High Byte
PWM1H.7
PWM1H.6
0
0
R/W
R/W
PWM1H.5
0
R/W
PWM1H.4
0
R/W
PWM1H.3
0
R/W
PWM1H.2
0
R/W
PWM1H.1
0
R/W
PWM1H.0
0
R/W
PWM Cycle Width Low Byte (PWM1L)
SFR Address:
Power-On Default:
Bit Addressable:
Table 38. PWM1L: PWM Cycle Width Low Byte
PWM1L.7
PWM1L.6
B3H
00H
No
PWM1L.5
PWM1L.4
PWM1L.3
PWM1L.2
PWM1L.1
PWM1L.0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Mode 0
In Mode 0, the PWM is disabled, allowing P2.5 and P2.6 to be
used as normal digital I/Os.
Mode 1 (Single-Variable Resolution PWM)
In Mode 1, both the pulse length and the cycle time (period) are
programmable in user code, allowing the resolution of the PWM
to be variable. PWM1H/L sets the period of the output waveform.
Reducing PWM1H/L reduces the resolution of the PWM output
but increases the maximum output rate of the PWM. For
example, setting PWM1H/L to 65536 gives a 16-bit PWM with
a maximum output rate of 192 Hz (12.583 MHz/65536). Setting
PWM1H/L to 4096 gives a 12-bit PWM with a maximum
output rate of 3072 Hz (12.583 MHz/4096).
PWM0H/L sets the duty cycle of the PWM output waveform as
shown in Figure 39.
P2.6
PWM COUNTER
PWM1H/L
0
PWM0H/L
0
Figure 39. PWM in Mode 1
Mode 2 (Twin 8-Bit PWM)
In Mode 2, the duty cycle and the resolution of the PWM
outputs are programmable. The maximum resolution of the
PWM output is 8 bits.
PWM1L sets the period for both PWM outputs. Typically, this is
set to 255 (FFH) to give an 8-bit PWM, although it is possible to
reduce this as necessary. A value of 100 could be loaded here to
give a percentage PWM, that is, the PWM is accurate to 1%.
The outputs of the PWM at P2.5 and P2.6 are shown in Figure 40.
As can be seen, the output of PWM0 (P2.5) goes low when the
PWM counter equals PWM0L. The output of PWM1 (P2.6) goes
high when the PWM counter equals PWM1H and goes low
again when the PWM counter equals PWM0H. Setting PWM1H
to 0 ensures that both PWM outputs start simultaneously.
P2.6
P2.5
PWM COUNTER
PWM1H
0
PWM1L
PWM0H
PWM0L
0
Figure 40. PWM Mode 2
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