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參數(shù)資料
型號(hào): ADUC845
廠商: Analog Devices, Inc.
元件分類: ADC
英文描述: MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU
中文描述: MicroConverter的多通道ADC的24-/16-Bit與嵌入式62 kB閃存以及單周期控制器
文件頁(yè)數(shù): 95/108頁(yè)
文件大小: 1109K
代理商: ADUC845
ADuC845/ADuC847/ADuC848
TIMING SPECIFICATIONS
AC inputs during testing are driven at DV
DD
– 0.5 V for Logic 1 and 0.45 V for Logic 0. Timing measurements are made at V
IH
min for
Logic 1 and V
IL
max for Logic 0 as shown in Figure 71.
Rev. A | Page 95 of 108
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a
100 mV change from the loaded V
OH
/V
OL
level occurs as shown in Figure 71.
C
LOAD
for all outputs = 80 pF, unless otherwise noted.
AV
DD
= 2.7 V to 3.6 V or 4.75 V to 5.25 V, DV
DD
= 2.7 V to 3.6 V or 4.75 V to 5.25 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 64. CLOCK INPUT (External Clock Driven XTAL1) Parameter
t
CK
XTAL1 Period
t
CKL
XTAL1 Width Low
t
CKH
XTAL1 Width High
t
CKR
XTAL1 Rise Time
t
CKF
XTAL1 Fall Time
1/t
CORE
Core Clock Frequency
1
t
CORE
Core Clock Period
2
t
CYC
Machine Cycle Time
3
32.768 kHz External Crystal
Typ
30.52
6.26
6.26
9
9
1.57
0.636
0.636
Unit
μs
μs
μs
ns
ns
MHz
μs
μs
Min
0.098
10.2
Max
12.58
0.08
1
ADuC845/ADuC847/ADuC848 internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 12.58 MHz internal clock
for the system. The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.
2
This number is measured at the default Core_Clk operating frequency of 1.57 MHz.
3
ADuC845/ADuC847/ADuC848 machine cycle time is nominally defined as 1/Core_Clk.
DV
DD
– 0.5V
0.45V
0.2DV
+ 0.9V
TEST POINTS
0.2DV
DD
– 0.1V
V
LOAD
– 0.1V
V
LOAD
V
LOAD
+ 0.1V
TIMING
REFERENCE
POINTS
V
LOAD
– 0.1V
V
LOAD
V
LOAD
– 0.1V
0
Figure 71. Timing Waveform Characteristics
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