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參數資料
| 型號： | ADUC845 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| 中文描述： | MicroConverter的多通道ADC的24-/16-Bit與嵌入式62 kB閃存以及單周期控制器 |
| 文件頁數： | 54/108頁 |
| 文件大小： | 1109K |
| 代理商： | ADUC845 |
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ADuC845/ADuC847/ADuC848
Using the DAC
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier, the functional equivalent
of which is shown in Figure 33.
Rev. A | Page 54 of 108
OUTPUT
BUFFER
HIGH-Z
DISABLE
(FROM MCU)
R
R
R
R
R
AV
DD
V
REF
0
14
Figure 33. Resistor String DAC Functional Equivalent
Features of this architecture include inherent guaranteed
monotonicity and excellent differential linearity. As shown in
Figure 33, the reference source for the DAC is user-selectable in
software. It can be either AV
DD
or V
REF
. In 0 V-to-AV
DD
mode,
the DAC output transfer function spans from 0 V to the voltage
at the AV
DD
pin. In 0 V-to-V
REF
mode, the DAC output transfer
function spans from 0 V to the internal V
REF
(2.5 V). The DAC
output buffer amplifier features a true rail-to-rail output stage
implementation. This means that, unloaded, each output is
capable of swinging to within less than 100 mV of both AV
DD
and ground. Moreover, the DAC’s linearity specification (when
driving a 10 k resistive load to ground) is guaranteed through
the full transfer function except Codes 0 to 48 in 0 V-to-V
REF
mode and 0 to 100 and 3950 to 4095 in 0 V-to-V
DD
mode.
Linearity degradation near ground and V
DD
is caused by satura-
tion of the output amplifier; a general representation of its effects
(neglecting offset and gain error) is shown in Figure 34. The
dotted line indicates the ideal transfer function, and the solid
line represents what the transfer function might look like with
endpoint nonlinearities due to saturation of the output amplifier.
Note that Figure 34 represents a transfer function in 0-to-V
DD
mode only. In 0 V-to-V
REF
mode (with V
REF
< V
DD
), the lower
nonlinearity would be similar, but the upper portion of the
transfer function would follow the ideal line to the end, showing
no signs of the high-end endpoint linearity error.
V
DD
–50mV
V
DD
V
DD
–100mV
100mV
50mV
0mV
000H
FFFH
0
Figure 34. Endpoint Nonlinearities Due to Amplifier Saturation
The endpoint nonlinearities shown in Figure 34 become worse
as a function of output loading. Most data sheet specifications
assume a 10 k resistive load to ground at the DAC output. As
the output is forced to source or sink more current, the nonlinear
regions at the top or bottom, respectively, of Figure 34 become
larger. With larger current demands, this can significantly limit
output voltage swing. Figure 35 and Figure 36 illustrate this
behavior. Note that the upper trace in each of these figures is
valid only for an output range selection of 0 V to AV
DD
. In 0 V-
to-V
REF
mode, DAC loading does not cause high-side voltage
nonlinearities while the reference voltage remains below the
upper trace in the corresponding figure. For example, if AV
DD
=
3 V and V
REF
= 2.5 V, the high-side voltage is not affected by
loads of less than 5 mA. But around 7 mA, the upper curve in
Figure 36 drops below 2.5 V (V
REF
), indicating that at these
higher currents, the output is not capable of reaching V
REF
.
SOURCE/SINK CURRENT (mA)
5
0
5
10
15
O
4
3
2
1
0
DAC LOADED WITH 0000H
DAC LOADED WITH 0FFFH
0
Figure 35. Source and Sink Current Capability with V
REF
= AV
DD
= 5 V
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相關代理商/技術參數 |
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|---|---|
| ADUC845_12 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter?? Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
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| ADUC845BCP32-5 | 制造商:Analog Devices 功能描述:10 CHANNEL 24 BIT DUAL ADC + FAST 8BIT UP - Trays |
| ADUC845BCP62-3 | 制造商:Analog Devices 功能描述:MCU 8-bit ADuC8xx 8052 CISC 62KB Flash 3.3V/5V 56-Pin LFCSP EP |
| ADUC845BCP62-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
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