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參數資料
| 型號： | ADUC845 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| 中文描述： | MicroConverter的多通道ADC的24-/16-Bit與嵌入式62 kB閃存以及單周期控制器 |
| 文件頁數： | 66/108頁 |
| 文件大小： | 1109K |
| 代理商： | ADUC845 |
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ADuC845/ADuC847/ADuC848
USING THE SPI INTERFACE
Depending on the configuration of the bits in the SPICON
SFR shown in Table 41, the SPI interface transmits or receives
data in a number of possible modes. Figure 46 shows all
possible ADuC845/ADuC847/ADuC848 SPI configurations
and the timing relationships and synchronization among the
signals involved. Also shown in this figure is the SPI interrupt
bit (ISPI) and how it is triggered at the end of each byte-wide
communication.
Rev. A | Page 66 of 108
SCLOCK
(CPOL = 1)
SCLOCK
(CPOL = 0)
(CPHA = 1)
(CPHA = 0)
SAMPLE INPUT
ISPI FLAG
DATA OUTPUT
ISPI FLAG
SAMPLE INPUT
DATA OUTPUT
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
SS
0
Figure 46. SPI Timing, All Modes
SPI Interface—Master Mode
In master mode, the SCLOCK pin is always an output and
generates a burst of eight clocks whenever user code writes to
the SPIDAT register. The SCLOCK bit rate is determined by
SPR0 and SPR1 in SPICON. Also note that the SS pin is not
used in master mode. If the parts need to assert the SS pin on an
external slave device, a port digital output pin should be used.
In master mode, a byte transmission or reception is initiated by
a byte write to SPIDAT. The hardware automatically generates
eight clock periods via the SCLOCK pin, and the data is
transmitted via MOSI. With each SCLOCK period, a data bit is
also sampled via MISO. After eight clocks, the transmitted byte
is completely transmitted (via MOSI), and the input byte (if
required) is waiting in the input shift register (after being
received via MISO). The ISPI flag is set automatically, and an
interrupt occurs if enabled. The value in the input shift register
is latched into SPIDAT.
SPI Interface—Slave Mode
In slave mode, the SCLOCK is an input. The SS pin must also be
driven low externally during the byte communication. Trans-
mission is also initiated by a write to SPIDAT. In slave mode, a
data bit is transmitted via MISO, and a data bit is received via
MOSI through each input SCLOCK period. After eight clocks,
the transmitted byte is completely transmitted, and the input
byte is waiting in the input shift register. The ISPI flag is set
automatically, and an interrupt occurs, if enabled. The value in
the shift register is latched into SPIDAT only when the trans-
mission/reception of a byte has been completed. The end of
transmission occurs after the eighth clock has been received if
CPHA = 1, or when SS returns high if CPHA = 0.
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| ADUC845BCP8-5 | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
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相關代理商/技術參數 |
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| ADUC845_12 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter?? Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| ADUC845BCP32-3 | 制造商:Analog Devices 功能描述:10 CHANNEL 24 BIT DUAL ADC + FAST 8BIT UP - Trays |
| ADUC845BCP32-5 | 制造商:Analog Devices 功能描述:10 CHANNEL 24 BIT DUAL ADC + FAST 8BIT UP - Trays |
| ADUC845BCP62-3 | 制造商:Analog Devices 功能描述:MCU 8-bit ADuC8xx 8052 CISC 62KB Flash 3.3V/5V 56-Pin LFCSP EP |
| ADUC845BCP62-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
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